Intel Xeon Phi 50 Core Co-Processor (B0 Stepping) Detailed

Hassan Mujtaba
Posted 4 years ago

VR-Zone has detailed some interesting bits of Intel’s Xeon Phi (Knights Corner) 50 Core Co-processor which would be aimed towards the HPC (High-Performance-Computing) segment.

Intel Knights Corner is manufactured on the 22nm process node featuring Tri-Gate transistors architecture same as the one used on Ivy Bridge processors. According to the details, Xeon Phi has entered the B0 stepping and comes in three different versions with variable configurations.

57C, 60C and 61 core versions have been detailed each featuring 1.8-1.9MB of L1 and 28-30.5MB of L2 cache. Total on-board memory varies from  3GB, 6GB and 8GB of GDDR5 memory of each part.

The minimum clock speeds are as follows:

  • 600 MHz (57C/3GB and 57C/6GB)
  • 630+ MHz (60C/8GB and two 61C/8GB)

Memory clock is set around 5 – 5.5GHz (1.25-1.37GHz Quad Data Rate) on a 512-bit interface which allows in an bandwidth of 300GB/s+. Maximum core clock is 1.1GHz for 57C/3GB and 57C/6GB parts and 1.05 to 1.09GHz for the other cards, Turbo Boost is also present but no exact details were acquirable.

TDP of 57C/3GB and 60C/6GB ranges between 245W while 300W for 57C/6GB and two 61C/8GB and each model is available with or without passive heatsinks. The Knights corner active heatsink was only available with the 57C/6GB/300W model while others were kept bare for liquid cooling testing like the one Intel recently used on SB-E by OEM CoolIT.

With the Xeon Phi, Intel might just have a chance to go against the upcoming NVIDIA’s K20 (GK110 GPU, 2880 cores, 384-bit memory interface, 12GB GDDR5) and AMD’s Firepro W9000 Professional HPC parts.

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