TSMC’s 3nm Wafer Prices Will Erode Transistor Density Cost Gains Worries Morgan Stanley
The Taiwan Semiconductor Manufacturing Company (TSMC) has received a downgrade rating from investment bank Morgan Stanley due to the fab's capital expenditure for the coming years. TSMC, which is the world's premium contract chip manufacturer, plans to invest $100 billion over the next three years due to its plans of aggressively developing leading-edge chip manufacturing process nodes. In its latest report, Morgan Stanley has cut TSMC target share price to NT$ 580 from an earlier NT$ 655 and downgraded the stock's rating to Neutral, as it worries that aggressive capital expenditure will hurt the company's gross margins.
Morgan Stanley Fears The End Of Moore's Law Cost Advantage Will Make It Difficult For TSMC To Recover Capital Expenditure
The report, which came out yesterday, points out several reasons to downgrade TSMC's stock and cut down its target price. The fab is currently on track to produce its latest 3nm chip node next year and is currently supplying tech giants such as Apple Inc with products manufactured on the 5nm process. More importantly, TSMC also plans to customize its chip process nods as it looks to take Santa Clara, California-based American chip giant Intel Corporation head-on after the latter announced its plans for contract chip manufacturing earlier this year.
Morgan Stanley believes that while TSMC will grow faster than the chip sector, the market has overestimated this growth rate. Analyst Zhan Jiahong highlights that the extensive capital spending will harm TSMC's gross margins, which he believes will stand below 50% in the long term.
The margin stood at 52.4% in the first quarter of this year, and more importantly, while TSMC's revenues grew by 16.7% during the quarter, its product costs almost matched this growth by growing at 15.2%. Additionally, the revenues grew by a paltry 0.2% sequentially during the first quarter. Still, expenses grew by 3.8% - a natural phenomenon as while the first quarter is a slow season for TSMC, the fab starts ramping production to meet future orders.
The analyst also reiterates concerns shared earlier by other quarters that the chip sector is headed for a downturn later this year. Courtesy of the ongoing pandemic, which looks to enter its second anniversary in December, the demand for consumer electronics grew. This resulted in more demand for TSMC's products, and many analysts worry that a surplus of orders placed might put the industry in a glut later on. He believes that the fourth quarter will be crucial for the sector, as chip demand might drop following the aforementioned aggressive growth.
While many worry about the fate of the semiconductor sector, chip designers Advanced Micro Devices, Inc and NVIDIA Corporation are currently facing product shortages. NVIDIA's chief financial officer Ms. Collette Kress believes that these shortages will last through 2021, a statement she has made several times, both during this year and in 2020.
As advances in chip manufacturing allow fabs to put more transistors in a similar area through new manufacturing technologies, electronic devices often undergo a cost advantage that improves margins for chip manufacturers. TSMC and IBM's development of the 2nm chip node are considered the next step in this evolution (previously dubbed as Moore's Law). Still, Jiahong worries that the extensive capital expenditure needed to fund the new nodes shrinks this advantage.
Specifically, he cites the initial pricing of 3nm wafers as evidence that the cost of transistors has not decreased, implying that even though TSMC and others can squeeze in more of them inside a chip, the increasing costs will hurt their margins.
While he believes that TSMC's advanced packaging techniques will improve chip performance, this is only a stop-gap measure that prevents companies from migrating to the more expensive 3nm and 2nm process nodes.
At this point, it is interesting to note that a 2019 report by IBS Research predicted that while per-transistor costs will reduce for 3nm chips, overall wafer and chip die costs will increase. In its study, IBS had estimated that a single transistor part of a group of one billion would be $2.16, lower than the $2.25 for the 5nm process. The research firm also outlined that a 3nm wafer would cost $15,500 - a $3,000 increase over 5nm and that a die would cost $30.45, up from the previous generation's $23.57.
In a presentation he gave during the International Solid-State Circuits Conference (ISSCC) earlier this year, TSMC's chairman Dr. Mark Liu highlighted that his company's 3nm process is on track to deliver a two year, 2x performance improvement. The fab's shares in Taiwan are up by more than 6% over the past thirty days, and its American Depositary Receipts (NYSE:TSM) is down by 2.5% today.
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