TSMC’s 3nm Process On Track For 2 Year, 2X Performance Improvement – Chairman

Ramish Zafar

This is not investment advice. The author has no position in any of the stocks mentioned. Wccftech.com has a disclosure and ethics policy.

The Taiwan Semiconductor Manufacturing Company's (TSMC) chairman Dr. Mark Liu has confirmed that the company's next-generation 3nm chip manufacturing node is on schedule. TSMC, which supplies processors to customers all over the world is currently building a facility to manufacture 3nm chips, and the company hopes to commence production for these products next year.  

TSMC's 3nm Will Nearly Double Logic Density Over Its 5nm Node and Deliver an 11% Performance Boost or 27% Power Efficiency Gain

The executive's comments regarding his company's next manufacturing technology confirm that TSMC believes that it will be able to manage both the increased demand for its current and future products at the same time - without letting the recent uptick in demand for automobile products affect its output. They came during his talk at the International Solid-State Circuits Conference (ISSCC) titled 'Unleashing the Future of Innovation' given on Monday last week.

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Importantly, they were also misconstrued by media outlets to claim that Dr. Liu had stated that the 3nm process was ahead of schedule. However, his 27-minute presentation did not state any such fact, with the only comments for 3nm's development schedule coming near the start and the end of his talk.

An excerpt from Dr. Liu's presentation showing the gains of 3nm over 5nm. Image: Unleashing the Future of Innovation/ISSC 2021

Apart from stating that "By the way, 3nm technology development is making good progress and well on our schedule", Dr. Liu also provided the latest figures for the 3nm process and his thoughts about the current state of process development. Additionally, he also highlighted that to date, TSMC has shipped roughly 1.8 billion chips manufactured on the company's 7nm process node - which until last year, was at the very top of the company's process technology food chain.

According to him, extreme ultraviolet (EUV) lithography has enabled TSMC to achieve higher patterning fidelity, shorter cycle times and reduced process complexity and defect rates. Additionally, according to Dr. Liu, his company uses EUV in ten mask layers for the 5nm node. Specifically, it's used at the line cut, contact and metal line patterning, with single-layer EUV patterning replacing multiple layers of earlier technologies that use deep ultraviolet (DUV) lithography.

During his talk, Dr. Liu highlighted Design Technology Co-optimization as being used to improve logic density and die costs. Image: Unleashing the Future of Innovation/ISSC 2021

TSMC's chairman then proceeded to highlight how Design Technology Co-optimization (DTCO) has become increasingly important over the course of the past few years for chip manufacturing. DTCO, which allows chip manufacturers to use both design and manufacturing technologies for keeping up with performance requirements, has enabled TSMC to move beyond intrinsic scaling metrics like contact gate pitch and minimum metal pitch when measuring the logic density of a node. Instead, following DTCO, features such as gate-contact over active area, single diffusion breaks and fin-depopulation to deliver the 1.8X logic density for 3nm over 5nm.

He also highlighted his company's plans for the future which include developing low-dimensional (sub-3D) materials such as growing a single crystal hexagonal Boron-nitride on  wafer-scale. This channel and materials can be transferred to arbitrary substrates at low fabrication temperatures, opening avenues for fabricating active logic and memory layers in three dimensions, according to the executive.

TSMC's research into low-dimensional materials also includes looking into 1D carbon nanotubes.  A key problem with transistor channels using carbon nanotubes is the need to develop a gate dielectric material that allows transistors with a short gate length. According to Dr. Liu, research has shown that this is now possible, with the material (shown above) capable of a high-k gate stack suitable to manufacture transistors with 10nm gate length.

He concluded by stressing the need for a close cooperation amongst all sectors of the chip industry to ensure that the current trend which results in a new chip manufacturing process to deliver 2x energy efficient performance every two years. TSMC's 5nm process (currently in mass production) follows this trend, and the upcoming 3nm node is also on track to follow the historical timeline stated Dr. Liu.

Semiconductor manufacturing processes have become a crucial topic for policymakers all over the globe as a growing demand for silicon places record demand for firms such as TSMC. This demand has currently resulted in manufacturing disruptions for automakers, as they face a chip shortage.

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