TSMC Taking First Steps To Build Its 1.4nm Facility In Taiwan By End Of 2025, Will Not Adopt ASML’s High-NA EUV Machines For This Process

Omar Sohail
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Image Credits: TSMC

It is pretty much confirmed that TSMC will begin 2nm wafer production by the end of 2025, but the world’s biggest semiconductor manufacturer aims to maintain its dominant lead by pursuing a manufacturing process even lower than the aforementioned lithography; 1.4nm, which is also known as A14. According to the latest report, the company will commence the very first steps of 1.4nm wafer production on its local turf, but will seemingly not rely on ASML’s cutting-edge and ludicrously expensive High-NA EUV machinery.

Instead of using High-NA EUV equipment of the 1.4nm process, TSMC will resort to complex multi-patterning techniques to achieve its goals

Even though Commercial Times reports that TSMC will break ground on its 1.4nm fabrication plant in Taichung by the end of this year, mass production is not expected until the second half of 2028. This manufacturing timeline has been shared previously, while also mentioning that the company’s A14 process can deliver up to a 30 percent reduction in power consumption.

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The R&D of the 1.4nm process will happen at TSMC’s plant in Hsinchu, with recruitment already happening at its Taichung facility. Construction permits for three buildings were issued in the month of August. To make its plans come to fruition, TSMC’s initial investment could reach a mammoth NT$1.5 trillion, or approximately $49 billion, of which a large portion will likely be allocated towards purchasing 30 EUV lithography machines in 2027.

Dan Nystedt says on this latest post on X that TSMC will not acquire any of ASML’s High-NA EUV equipment, likely due to the massive dollar amount attached to these machines. At $400 million apiece, it is an expensive undertaking for TSMC, with the latter previously saying that its current hardware is capable of mass producing 1.4nm wafers. The Taiwanese semiconductor behemoth will probably resort to complex multi-patterning techniques, similar to what SMIC employs to develop its 5nm process.

The drawbacks of this alternative are that it is time-consuming and costly, and will not ensure a satisfactory yield at first, forcing TSMC to switch to a ‘trial and error’ approach to gradually improve its 1.4nm process. However, the biggest difference between TSMC and SMIC is that the former already possesses specialized EUV equipment to make this possible, and since the mass production timeline is still a few years away, it has plenty of time to perfect the cutting-edge node.

News Source: Commercial Times

Omar Sohail Photo

About the author: Omar Sohail is a reporter and analyst for Wccftech's mobile section, specializing in the technology and business of the mobile industry. His expertise lies in the intricate hardware supply chain, covering developments in semiconductor manufacturing, chip lithography, and camera sensor technology.

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