TSMC’s In A Rush To Take The Lead; Commences 3nm Plant Construction In Taiwan

Oct 30, 2019
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Last week, Taiwanese sources reported that TSMC had finalized land acquisition plans to build a 3nm fabrication plant in Taiwan. The company has been pushed to the forefront of the tech world through its partnership with American heavyweights Advanced Micro Devices and Apple Inc. Now, soon after TSMC's land acquisition plans were finalized, it's being reported that the company has started constructing the new facility. Take a look below for more details.

TSMC Starts Constructing 3nm Fabrication Facility In Taiwan After Acquiring Land Earlier

Judging its CEO's statements given during TSMC's latest earnings call, the fab plans to aggressively scale up 5nm next year. The company's current bleeding-edge semiconductor fabrication process is 7nm+ which using extreme ultraviolet light for patterning. This allows TSMC to etch circuits far finer than those printed through traditional diffusion-based lithography.

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However, while TSMC's got 5nm on its mind, the company hasn't forgotten the future. After 5nm chips are (hopefully) introduced next year, companies will refine the process for two more years before shifting to 3nm in 2020. And TSMC's construction plans seem to keep this timeline in mind.

According to Feng, TSMC has commenced construction on the 30-hectare land that it acquired last week for a new 3nm facility. This facility will cost the company $19.5 billion, and it will be operational in three years from now. Should things proceed normally, then chips fabricated through this process should feature on Apple's iPhones as well; but whether the processors are cost-effective is another debate.

Taking a look at data from IBS research, it appears as if 3nm chips will allow Apple to squeeze 4 billion additional transistors on a similarly sized 85mm² chip. This density increase will, however, come at an added cost of $3,000, pushing die cost to $30.45 for 3nm from $23.47 for the 5 nm fabrication process. Performance estimates for 3nm aren't available right now since TSMC has made public only its expected improvements for 5nm. This process will let the fab cram in 173 million transistors-per-mm², allowing for either a 15% performance boost or 30% power consumption improvement over the non-EUV 7nm node. Front and back-end 5nm improvements, dubbed as N5P will further eke out a 7% performance or a 15% power efficiency gain.

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