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The Taiwan Semiconductor Manufacturing Company (TSMC) has achieved an important breakthrough in its research and development for the 2nm semiconductor manufacturing node. Reports of this breakthrough have surfaced on the Taiwanese media, and have been picked up by Eastern media outlets. TSMC, which is responsible for supplying processors and other chips to a variety of big and small companies all over the world is also expected to enter trial production of this process in mid-2023 and commence mass production a year later.
TSMC's 2nm Node Will Mark Major Jump Over Current Chip Fabrication Technologies
Currently, TSMC's latest manufacturing node is its first-generation 5nm process that will be used to build processors for Apple's flagship smartphones for 2020. In layman terms, a 'node' refers to the dimensional measurement of a transistor's 'fin'. A modern-day processor consists of billions of such fins, which have enabled computing to reach unparalleled sophistication, cost-reduction and performance.
As opposed to a 'FinFET' (Fin Field Effect Transistor), which a term used to describe the design of a transistor on products built by TSMC and South Korea chaebol Samsung Electronic's Samsung Foundry arm, TSMC's 2nm process will utilize a difference transistor design. This design is termed as Multi-Bridge Channel Field Effect (MBCFET) transistor and it adds on to the previous FinFET designs.
A FinFET design involves three essential elements. These are the source, a gate and a drain, with the electrons making their way from the source to the grain and the gate regulating this flow. Designs prior to FinFET involved the source and the drain being fabricated only in the horizontal axis i.e. they lay flat with the chip in question.
FinFET's innovative approached raised both the source and the drain in the third dimension i.e. vertically, and as a result, it allowed for more electrons to pass through the gate, reduced leakage and reduced operating voltage.
TSMC's decision to use an MBCFET design for its transistors will not be the first time a foundry will have made this decision. Samsung announced the design for its 3nm manufacturing process in April last year, and the company's MBCFET design was an evolution over its GAAFET transistors that it jointly developed and introduced with IBM in 2017. Samsung's MBCFET, as opposed to its GAAFET, uses a nanosheet for the source and drains (the channel), with the former using nanowires instead. This increases the surface area that is available for conduction and more importantly, it allows the designer to add more gates to the transistor without increasing lateral surface area.
Unsourced statements floating around in the press also suggest that TSMC expects yield rate for its 2nm process node to reach a staggering 90% in 2023. If this occurs, then the fab will be well on its way to refine its manufacturing processes and comfortably switch to volume and mass production in 2024. Samsung, at the time of its MBCFET announcement, had stated that it expected the 3nm transistors to reduce power consumption by 30% and 45% respectively and improve performance by 30% over 7nm designs.
Whether TSMC's 2nm process will also deliver similar improvements is uncertain, but we should find out more once design parameters for the process have been finalized. IBM and Samsung's 5nm GAAFET design was able to squeeze an astonishing 30 billion transistors in a 50mm² surface area, and based on this, the sky truly appears to be the limit for TSMC.