NVIDIA has disclosed the first real information about its next-generation Rosa CPU, which will be coupled with its Feynman lineup.
NVIDIA Rosa CPU Extends Vera's Per-Core Leadership With A New Core Architecture, Larger Cache, & Better Instruction Delivery
At GTC 2026, NVIDIA disclosed its next-gen Data Center CPU, called Rosa. The Rosa CPU will be launching alongside Feynman and will be precisely optimized for Agentic AI workloads as those continue to demand increased processing performance. Rosa is named after American physicist & a Nobel Prize winner, Rosalyn Sussman.
Today, NVIDIA confirms more details of its next-generation Rosa CPU, and these are some big ones. Starting with the most important detail, NVIDIA has said that its Rosa CPUs will utilize a brand new core architecture called "Rigel," which is based on the Arm v9.2 CPU core. Like Vera, Rosa will be a really fast chip for AI processing, achieving even more "max single-threaded" CPU performance at scale than its predecessor.
While Vera utilizes the Olympus cores, which are custom Armv9.2-A cores that offer 2x the throughput versus Grace, Rosa will take the single-core performance advantage even further. What's more impressive is that the performance uplift will be achieved in the same silicon footprint.
NVIDIA’s next-generation Rosa CPU with the Rigel core will continue the company’s CPU roadmap for the agentic AI era. Rigel is NVIDIA’s next-generation Arm v9.2 CPU core, delivering higher per-core performance than Olympus while keeping the same silicon footprint. Key improvements include better instruction delivery, a larger L2 cache, and more efficient memory handling.
via NVIDIA
Coming to additional details, NVIDIA highlights improvements in the form of better instruction delivery, a larger L2 cache, and more efficient memory handling. Currently, Vera is equipped with 88 Olympus cores, up from 72 cores on Grace. It isn't mentioned if Rosa comes with a core count increase.
Key Specifications Comparison
| Feature | Grace CPU | Vera CPU | Rosa CPU |
|---|---|---|---|
| Status / Availability | Shipping (since 2023) | In production (2026, powers Vera Rubin systems) | Expected 2028 (with Feynman GPUs) |
| Core Architecture | Arm Neoverse V2 (Armv9, licensed) | Custom NVIDIA Olympus (Armv9.2, in-house) | Custom NVIDIA Rigel (Armv9.2, in-house) |
| Cores per CPU | 72 | 88 | TBD |
| Threads per CPU | 72 | 176 (via Spatial Multithreading) | TBD |
| IPC / Per-Core Perf | Baseline (Neoverse V2) | ~50% higher IPC than Grace (Olympus) | Higher per-core than Olympus; focus on ultimate single-thread performance |
| L2 Cache per Core | 1 MB | 2 MB (double Grace) | Larger than Olympus (explicit improvement) |
| Memory Type | LPDDR5X with ECC | LPDDR5X with ECC + SOCAMM / LPDDR6 (RTX Spark) | LPDDR6 / LPDDR6X (RTX Spark)? |
| Memory Bandwidth | Up to ~480–512 GB/s per CPU | Up to 1.2 TB/s (2–3× higher per core vs leading x86) | TBD (expected further gains in efficiency) |
| Memory Capacity | Up to ~480–512 GB per CPU | Up to 1.5 TB | TBD |
| Die Design | Monolithic per CPU (Superchip pairs two via NVLink-C2C) | Monolithic compute die (avoids chiplet latency) | TBD (likely monolithic evolution) |
| Key Interconnect | 1st-gen SCF; NVLink-C2C 900 GB/s (Superchip) | 2nd-gen SCF (3.4 TB/s bisection); NVLink-C2C up to 1.8 TB/s | TBD (further improvements expected) |
| Power Efficiency Focus | 2× performance at the same power vs leading x86 (at launch) | High sustained per-core perf + low memory power (<40W for memory subsystem in some configs) | Ultimate single-thread efficiency |
| Primary Design Goal | Balanced high-core-count efficiency for accelerated/HPC workloads | Max single-threaded performance at scale for agentic AI loops | Ultimate single-thread performance (evolution of Vera's philosophy) |
Looking at Rosa and NVIDIA's handling of its CPU architectures with Grace and now Vera, the company has come a long way, tackling x86 competitors directly in the AI space. Vera is already in full production and is now shipping Vera Rubin and Standalone racks to major AI firms across the globe. The NVIDIA CPU strategy stretches beyond Enterprise and Data Centers, as the same cores will be housed by next-generation RTX Spark chips.
The first of the RTX Spark chips are expected this fall, bringing Grace and Blackwell together with 2028's lineup focusing on Vera Rubin combos, and finally, Rosa should enter the market by 2029 in data centers, followed by PC-specific variants in the Rosa Feynman Spark solutions by 2030.
NVIDIA Data Center / AI GPU Roadmap
| GPU Codename | Feynman | Rubin (Ultra) | Rubin | Blackwell (Ultra) | Blackwell | Hopper | Ampere | Volta | Pascal |
|---|---|---|---|---|---|---|---|---|---|
| GPU Family | GF200? | GR300? | GR200? | GB300 | GB200/GB100 | GH200/GH100 | GA100 | GV100 | GP100 |
| GPU SKU | F200? | R300? | R200? | B300 | B100/B200 | H100/H200 | A100 | V100 | P100 |
| Process Tech | TSMC A16? | TSMC N2P? | TSMC N3P? | TSMC 4NP | TSMC 4NP | TSMC 5nm | TSMC 7nm | TSMC 12nm | TSMC 16nm |
| CPU | Rosa | Vera | Vera | Grace | Grace | Grace | N/A | N/A | N/A |
| Memory | HBM4e/HBM5? | HBM4 | HBM4 | HBM3e | HBM3e | HBM2e/HBM3/HBM3e | HBM2e | HBM2 | HBM2 |
| Launch | 2028 | 2027 | 2026 | 2025 | 2024 | 2022-2024 | 2020-2022 | 2018 | 2016 |
About the author: A Software Engineer by training and a PC enthusiast by passion, Hassan Mujtaba serves as Wccftech's Senior Editor for hardware section. With years of experience in the industry, he specializes in deep-dive technical analysis of next-generation CPU and GPU architectures, motherboards, and cooling solutions. His work involves not only breaking news on upcoming technologies but also extensive hands-on reviews and benchmarking.
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