Intel Unveils ‘Foveros’, A Brand New Way To 3D Stack Chips With An Active Interposer
Intel unveiled a lot of details at the Architecture Day held yesterday and one of these juicy details include Foveros – Intel’s new approach to heterogeneous system integration. It’s the spiritual successor to Intel’s EMIB and features an active interposer to “mix and match” pretty much any IP together. The key differentiator here is the use of an active interposer as opposed to a passive interposer.
Intel unveils Foveros 3D die stacking technology
Foveros paves the way for devices and systems combining high-performance, high-density and low-power silicon process technologies. Foveros is expected to extend die stacking beyond traditional passive interposers and stacked memory to high-performance logic, such as CPU, graphics and AI processors for the first time.
The technology provides tremendous flexibility as designers seek to “mix and match” technology IP blocks with various memory and I/O elements in new device form factors. It will allow products to be broken up into smaller “chiplets,” where I/O, SRAM and power delivery circuits can be fabricated in a base die and high-performance logic chiplets are stacked on top.
Intel expects to launch a range of products using Foveros beginning in the second half of 2019. The first Foveros product will combine a high-performance 10nm compute-stacked chiplet with a low-power 22FFL base die. It will enable the combination of world-class performance and power efficiency in a small form factor.
Foveros is the next leap forward following Intel’s breakthrough Embedded Multi-die Interconnect Bridge (EMIB) 2D packaging technology, introduced in 2018.
So why the need for 3D stacking? Well, as Intel demonstrated in their presentation, no single transistor node works across all types of applications. For iGPU you need minimal leakage with low power and low cost, with dGPU you need a mix of performance, power, and cost while for desktop CPUs you need high performance (at a high cost) and power consumption is tolerated. The only way to get an optimal design architecture that caters to all these facets is to connect everything together on an interposer.
This is where Foveros comes in, it is a very high density interconnect that enables the company to realize their vision of connecting chiplets in a package with the seamlessness of a monolithic die.
The layout of the Foveros design is as follows: the compute chip and other IP blocks are placed using FTF Micro-bumps on the active interposer through which TSVs (through silicon vias) are drilled to connect with solder bumps and eventually the final package. It looks pretty similar in design to the heterogenous design featured by AMD and comparisons are going to be completely inevitable.
Unlike AMD designs, however, the interposer in question here is actually a base compute die and will not be passive. This will allow unparalleled control over leakage and performance. Intel is also touting the worlds first “hybrid x86” architecture through the use of Foveros in its 2019 FPGA product.
Intel also mentioned how the future would require a mix of scalar, vector, matric and spatial architectures deployed in CPU, GPU, accelerator and GPGA sockets and Foveros is one of the first steps to take towards realizing that future. The company has also reiterated the lego-like, mix and match philosophy to building computer chips, which is something it has initially shied away from doing (sticking primarily to Monolithic dies) so it is incredibly exciting to see where this will lead us.