NVIDIA has presented its approach with next-gen AI accelerators, showcasing an innovative "silicon photonic" implementation at the IEDM 2024 conference.
NVIDIA's Vision Of Next-Gen AI Accelerators Includes Utilizing Silicon Photonics Interposers & Unique Stacking Methods
With modern-day packaging techniques, the industry has reached a point where there is a dire need for innovation, given that AI computing demands are increasing massively with time. Whenever there's a discussion about the future of packaging, silicon photonics (SiPh) is an approach deemed a viable alternative to conventional methods. Interestingly, at the IEDM 2024 conference, Team Green presented a unique strategy (via Ian Cutress) for next-gen accelerators, which involves using a SiPh interpose and stacking GPU tiles vertically for such a large compute product.
Here's @NVIDIA's vision of the future of AI compute.
Silicon photonics interposer
SiPh intrachip and interchip
12 SiPh connects, 3 per GPU tile
4 GPU tiles per tier
GPU 'tiers' (GPU on GPU?!?)
3D Stacked DRAM, 6 per tile, fine-grainedFrom #iedm24. My guess, 2028/2029/2030β¦ pic.twitter.com/5IsDkYSWT2
β π·π. πΌππ πΆπ’π‘πππ π (@IanCutress) December 8, 2024
Team Green's implementation proposes the integration of silicon photonics interposers, replacing the electrical interconnects out there. The utilization of SiPh brings in several benefits, likely in the form of providing higher bandwidth and lower latency, along with being a much more energy-efficient method than other methods. Not just the interposes, but NVIDIA plans to use 12 SiPh in intrachip and interchip communication, optimizing the data flow between individual GPU tiles, which is crucial for scalability and performance.
Interestingly, the GPU stacking technique appeals the most in NVIDIA's vision, since the firm has revealed the use of "3D stacking", or stacking multiple GPU tiles vertically, to increase chip density and reduce footprint. Team Green calls this configuration a "GPU tier," with four GPU tiles in one tier, all stacked in a vertical orientation, to reduce interconnect latency and maybe implement power gating since this will be a possibility here. It will not just be GPUs, but NVIDIA will also 3D-stack DRAM chips, six per tile.
While this sounds an optimistic approach, NVIDIA's vision holds several complexities, mainly with how "naive" silicon photonics technology actually is right now, given that it is a relatively newer standard. Team Green would need to see SiPh being in high-volume production before it sees any mainstream integration, and this happening will take a long time. Along with this, aggressive 3D stacking will make thermals a huge issue, forcing NVIDIA to integrate an intra-chip cooling solution, which hasn't surfaced up for now.
The analyst Ian Cutress sees this implementation occurring within the next five years, likely between 2028 and 2030, given the complexities involved in this process.
About the author: Muhammad Zuhair is a hardware and technology reporter for Wccftech, specializing in the semiconductor industry and the complex interplay between technology, manufacturing, and geopolitics. His coverage focuses on the corporate strategies and technological roadmaps of industry giants like TSMC, NVIDIA, Samsung, and Intel. Zuhair's expertise lies in deconstructing complex topics such as fabrication nodes (e.g., 2nm process), the economic impact of policies like the CHIPS Act, and the strategic development of AI infrastructure from NVIDIA, AMD and Intel.
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