Intel’s Next-Gen 10nm ESF Based Sapphire Rapids Xeon CPU Die Shot Unveils MCM Design & Up To 80 Cores In 4 Chiplets
New die shots of Intel's next-gen Sapphire Rapids Xeon CPUs have surfaced which show an MCM design that could house up to 80 cores. The leak comes from Bilibili and shows us an engineering sample of the upcoming chip.
Intel Sapphire Rapids Xeon CPU Die Shots Unveils MCM Design With 4 Chiplets
We did get a close-up look at Intel's 4th Gen Sapphire Rapids Xeon CPU dies last month but we didn't get to see what's underneath those dies. The leaker managed to expose each of the four chiplet dies on the main interposer. With all four chiplets exposed, we can see that underneath them is a 5x4 core configuration which means each die consists of up to 80 cores. However, the entire 80 core silicon will never be released to the public due to the mesh layout.
Theoretically, Intel's Sapphire Rapids-SP Xeon CPUs could feature a maximum of 72 cores and 144 threads but we know from previous leaks that the maximum configuration is going to end up at 56 cores and 112 threads. In the previous leak, the leaker stated that we were looking at an ES chip that featured a total of 60 cores (15 cores per die or a 5x3 layout) while the actual chip only had 56 cores (14 cores per die) enabled.
The CPU will additionally come in HBM configurations with up to 64 GB capacities (4 x 16 GB stacks) and will also feature DDR5 and PCIe 5.0 I/O onboard. Another interesting thing is that the LGA4677 chips will feature a gold-plated IHS and feature a soldered design with liquid-metal TIM. The IHS on the Sapphire Rapids chips is also brand new but the chip itself comes in the same rectangle shape that we have seen on previous Xeon offerings.
Here's Everything We Know About Intel's 4th Gen Sapphire Rapids Xeon CPUs
The Sapphire Rapids-SP family will be replacing the Ice Lake-SP family and will go all on board with the 10nm Enhanced SuperFin process node that will be making its formal debut later this year in the Alder Lake consumer family. From what we know so far, Intel's Sapphire Rapids-SP lineup is expected to utilize the Golden Cove architecture & will be based on the 10nm Enhanced SuperFin process node.
The Sapphire Rapids lineup will make use of 8 channel DDR5 memory with speeds of up to 4800 MHz and support PCIe Gen 5.0 on the Eagle Stream platform. The Eagle Stream platform will also introduce the LGA 4677 socket which will be replacing the LGA 4189 socket for Intel's upcoming Cedar Island & Whitley platform which would house Cooper Lake-SP and Ice Lake-SP processors, respectively. The Intel Sapphire Rapids-SP Xeon CPUs will also come with CXL 1.1 interconnect that will mark a huge milestone for the blue team in the server segment.
Coming to the configurations, the top part is started to feature 56 cores with a TDP of 350W. What is interesting about this configuration is that it is listed as a low-bin split variant which means that it will be using a tile or MCM design. The Sapphire Rapids-SP Xeon CPU will be composed of a 4-tile layout with each tile featuring 14 cores each.
It looks like AMD will still hold the upper hand in the number of cores & threads offered per CPU with their Genoa chips pushing for up to 96 cores whereas Intel Xeon chips would max out at 56 cores if they don't plan on making SKUs with a higher number of tiles. Intel will have a wider and more expandable platform that can support up to 8 CPUs at once so unless Genoa offers more than 2P (dual-socket) configurations, Intel will have the lead in the most number of cores per rack with an 8S rack packing up to 448 cores and 896 threads.
The Intel Saphhire Rapids CPUs will contain 4 HBM2 stacks with a maximum memory of 64 GB (16GB each). The total bandwidth from these stacks will be 1 TB/s. According to leaked details from AdoredTV, HBM2 and GDDR5 will be able to work together in flat, caching/2LM, and hybrid modes. The presence of memory so near to the die would do absolute wonders for certain workloads that require huge data sets and will basically act as an L4 cache.
Intel is focusing on a launch for its Sapphire Rapids Xeon Scalable family in 2022 but a volume ramp is not expected until early 2022.
Intel Xeon SP Families (Preliminary):
|Family Branding||Skylake-SP||Cascade Lake-SP/AP||Cooper Lake-SP||Ice Lake-SP||Sapphire Rapids||Emerald Rapids||Granite Rapids||Diamond Rapids|
|Process Node||14nm+||14nm++||14nm++||10nm+||Intel 7||Intel 7||Intel 3||Intel 3?|
|Platform Name||Intel Purley||Intel Purley||Intel Cedar Island||Intel Whitley||Intel Eagle Stream||Intel Eagle Stream||Intel Mountain Stream|
Intel Birch Stream
|Intel Mountain Stream
Intel Birch Stream
|Core Architecture||Skylake||Cascade Lake||Cascade Lake||Sunny Cove||Golden Cove||Raptor Cove||Redwood Cove?||Lion Cove?|
|IPC Improvement (Vs Prev Gen)||10%||0%||0%||20%||19%||8%?||35%?||39%?|
|MCP (Multi-Chip Package) SKUs||No||Yes||No||No||Yes||Yes||TBD (Possibly Yes)||TBD (Possibly Yes)|
|Socket||LGA 3647||LGA 3647||LGA 4189||LGA 4189||LGA 4677||LGA 4677||TBD||TBD|
|Max Core Count||Up To 28||Up To 28||Up To 28||Up To 40||Up To 56||Up To 64?||Up To 120?||Up To 144?|
|Max Thread Count||Up To 56||Up To 56||Up To 56||Up To 80||Up To 112||Up To 128?||Up To 240?||Up To 288?|
|Max L3 Cache||38.5 MB L3||38.5 MB L3||38.5 MB L3||60 MB L3||105 MB L3||120 MB L3?||240 MB L3?||288 MB L3?|
|Memory Support||DDR4-2666 6-Channel||DDR4-2933 6-Channel||Up To 6-Channel DDR4-3200||Up To 8-Channel DDR4-3200||Up To 8-Channel DDR5-4800||Up To 8-Channel DDR5-5600?||Up To 12-Channel DDR5-6400?||Up To 12-Channel DDR6-7200?|
|PCIe Gen Support||PCIe 3.0 (48 Lanes)||PCIe 3.0 (48 Lanes)||PCIe 3.0 (48 Lanes)||PCIe 4.0 (64 Lanes)||PCIe 5.0 (80 lanes)||PCIe 5.0 (80 Lanes)||PCIe 6.0 (128 Lanes)?||PCIe 6.0 (128 Lanes)?|
|TDP Range (PL1)||140W-205W||165W-205W||150W-250W||105-270W||Up To 350W||Up To 375W?||Up To 400W?||Up To 425W?|
|3D Xpoint Optane DIMM||N/A||Apache Pass||Barlow Pass||Barlow Pass||Crow Pass||Crow Pass?||Donahue Pass?||Donahue Pass?|
|Competition||AMD EPYC Naples 14nm||AMD EPYC Rome 7nm||AMD EPYC Rome 7nm||AMD EPYC Milan 7nm+||AMD EPYC Genoa ~5nm||AMD Next-Gen EPYC (Post Genoa)||AMD Next-Gen EPYC (Post Genoa)||AMD Next-Gen EPYC (Post Genoa)|
News Source: HXL