Intel Details 15-Core Xeon E7 Ivytown and Haswell Microarchitecture Details at ISSCC 2014

At ISSCC 2014, Intel shared some new details regarding their upcoming Xeon E7 chip called Ivytown and the existing Haswell microarchitecture. Its surprising to see that so many details about Haswell were kept under wraps which have been revealed now such as the various die sizes of the chips and integrated graphics tech.Haswell Microarchitecture Die

Intel Haswell Microarchitecture Secrets Unveiled at ISSCC 2014

Intel's Haswell microarchitecture made its debut last year in June 2013 based on a completely new architecture developed on a 22nm 3D Tri-gate process technology. The Haswell lineup consisted of several SKUs ranging from dual core to quad core ULT, ULP, SOC and desktop models. The base transistor count ranges from 0.96 to 1.7 billion transistors with die sizes of 130mm2 upto 260mmand clock frequencies ranging from 1.1 GHz upto 3.8 GHz on the top most desktop model (Core i7-4770K). Following table gives a better comparison between the specifications of these SKUs (courtesy of Anandtech):

CPU Configuration GPU Configuration Die Size Transistor Count
4+3 Quad-Core GT3e 260mm2
1.7B + TBA
ULT 2+3 Dual-Core GT3 181mm2 1.3B
ULT 2+2 Dual-Core GT2 TBA ~1B
4+2 Quad-Core GT2 177mm2 1.4B
2+2 Dual-Core GT2 130mm2 0.96B

Talking about the desktop SKUs, the top most Core i7-4770K comes with up to four cores which share the same L3 cache. It features 1.6 Billion transistors and a die size of 177mm2. The Ivy Bridge die featured 1.4 Billion transistors in a 160mm2 die. A large portion of the die is dedicated to the Intel’s HD graphics in Haswell processors which also shares the same L3 cache. Other than these, the Haswell die include system agent, display agent, Memory controller I/O and PCI-e 3.0 memory controller.

The ULT models were specifically designed with On Package I/O which enables multi-chip packages to enable on-die eDRAM and PCH for SOC type SKUs. This helped to reduce the overall platform power consumption delivering small form factor solutions such as NUCs. In short, the OPIO (On Package I/O) is a low power single-ended and high bandwidth I/O link which enables MCPs. Haswell had two SKUs with the OPIO package, one featured an on-die PCH and had a 4 GB/s bandwidth using just 32mW power while the eDRAM variant had 102.4 GB/s bandwidth with 1W power input hence delivering higher bandwidth to the GPU core for faster performance.

Coming to eDRAM itself, Haswell is the first Intel microprocessor to feature the on die-eDRAM package which is codenamed Crystalwell. The package has a die size of 77mm2 with a 1V supply and clocked at 1.6 GHz. The chip has 128MB L4 eDRAM cache arranged into eight macros of 16 MB. The eDRAM helps drive performance upto 75% in gaming benchmarks which is an impressive development from Intel on the graphics front.Haswell eDRAM Crystalwell

Intel also implemented new deep package states to save power consumption on their Haswell SKUs. The ULT variants with 15W TDP have package states upto C10 which reduce power consumption down to 18mW through optimizations on the VR controller. Intel's Haswell microarchitecture is a power efficient architecture scaling several platforms with boosted graphics performance and has made a perfect path for Intel's future Broadwell core which arrives this year built on a 14nm process. Intel also detailed their Ivytown chip:


Intel's Xeon E7-8890 V2 ‘Ivy Town’ With 15 Cores and 4.31 Billion Transistors

Intel's upcoming Xeon E7 'Ivy Bridge-EX' lineup launches this year which delivers an unprecedented amounts of performance for HPC needs. Intel is preparing their flagship Xeon E7-8890 V2 chip codenamed Ivytown which is the first chip from Intel to boast a core count of 15 coming one step closer to AMD's Opteron 6300 series which has 16 cores on the top most model.

The chip features an insane 4.31 billion transistors and a massive die size of 541mmwith a modular architecture which splits the cores into blocks of three, each block has five cores with their own L3 cache, embedded ring bus and I/O. This modular architecture would scale from top to bottom of the Xeon E7 lineup with Intel shifting and removing the columns to offer cost effective SKUs. The chip features 37.5 MB L3 cache and a TDP of 155 Watts. According to the rumor mill, the flagship part could cost well over $5000 US. In an 8 Socket environment, eight of these chips would amount to 120 cores and 240 threads with a 300 MB cache shared via QPI v1.1. The frequency of the chip is toned down to 2.8 GHz but there are tons of models ranging in core configuration and clock speeds which can be found in the specification chart posted below along with the die shot of Ivytown (courtesy of Kitguru):

Intel Xeon E7 Ivy Town Die Shot:Intel Xeon E7 IvyTown Die

Intel Xeon E7 ‘Ivy Bridge-EX’ Lineup Specifications (Courtesy of CPUWorld):

Xeon E7 SKUs Cores /Threads Core Clock L3 Cache (LLC) Memory Support TDP
Xeon E7-2850 v2 12 / 24 2.3 GHz 24 MB DDR3-1333 105 Watt
Xeon E7-2870 v2 15 / 30 2.3 GHz 30 MB DDR3-1600 130 Watt
Xeon E7-2880 v2 15 / 30 2.5 GHz 37.5 MB DDR3-1600 130 Watt
Xeon E7-2890 v2 15 / 30 2.8 GHz 37.5 MB DDR3-1600 155 Watt
Xeon E7-4809 v2 6 / 12 1.9 GHz 12 MB DDR3-1066 105 Watt
Xeon E7-4820 v2 8 / 16 2 GHz 16 MB DDR3-1333 105 Watt
Xeon E7-4830 v2 10 / 20 2.2 GHz 20 MB DDR3-1333 105 Watt
Xeon E7-4850 v2 12 / 24 2.3 GHz 24 MB DDR3-1333 105 Watt
Xeon E7-4860 v2 12 / 24 2.6 GHz 30 MB DDR3-1600 130 Watt
Xeon E7-4870 v2 15 / 30 2.3 GHz 30 MB DDR3-1600 130 Watt
Xeon E7-4880 v2 15 / 30 2.5 GHz 37.5 MB DDR3-1600 130 Watt
Xeon E7-4890 v2 15 / 30 2.8 GHz 37.5 MB DDR3-1600 155 Watt
Xeon E7-8850 v2 12 / 24 2.3 GHz 24 MB  TBC 105 Watt
Xeon E7-8857 v2 12 / 24 3 GHz 30 MB DDR3-1333 130 Watt
Xeon E7-8870 v2 15 / 30 2.3 GHz 30 MB  TBC 130 Watt
Xeon E7-8880 v2 15 / 30 2.5 GHz 37.5 MB  TBC 130 Watt
Xeon E7-8880L v2 15 / 30 2.2 GHz 37.5 MB DDR3-1600 105 Watt
Xeon E7-8890 v2 15 / 30 2.8 GHz 37.5 MB  TBC 155 Watt
Xeon E7-8891 v2 10 / 20 3.2 GHz 37.5 MB DDR3-1600 155 Watt
Xeon E7-8893 v2 6 / 12 3.4 GHz 37.5 MB DDR3-1600 155 Watt
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