Intel's 18A is said to report an SRAM density equal to that of TSMC's N2 process, signaling a massive breakthrough for the IFS and its semiconductor ambitions.
Intel's 18A Process Is a "Special" One, Credits To Implementations Such As BSPDN Along With Years of R&D Behind It
Well, it seems like now might be the time to be bullish on the future of Intel's chip plans, since the latest reports are clearly indicating that the momentum is shifting towards Team Blue. Following the political backing of the Trump administration, it is now disclosed via ISSCC sessions (via Ian Cutress) that both TSMC and Intel's cutting-edge processes are rivaling each other in SRAM densities, showing that the gap has been narrowed down significantly, at least in one of the important aspects.
Sat in @ieee_isscc session 29: SRAM
1st paper: $TSM 38 Mb/mm2 N2 HD SRAM
2nd paper: $INTC 38 Mb/mm2 18A HD SRAM
3rd paper: @Mediatek 3nm TCAM
4th paper: @Synopsys 38 Mb/mm2 3nm HD SRAMIt's a battle royale.
— 𝐷𝑟. 𝐼𝑎𝑛 𝐶𝑢𝑡𝑟𝑒𝑠𝑠 (@IanCutress) February 19, 2025
We have discussed Intel's 18A in the past several times, but now might be one of the best times for an in-depth overview, given the hype around it. One of the more monumental achievements with Intel's 18A is the utilization of BSPDN (Backside Power Delivery), which is said to move the power delivery process to the backside of the wafer. This marks one of the industry's first implementations, and this mainly leads to improved power efficiency along with signal integrity, marking a massive breakthrough for the process in general.
Intel's 18A "high-density" versions are now said to report a macro bit density of 38.1 Mb/mm², that too with the large array configuration. Different arrangements of SRAM cells will bring in varied densities, but overall, things are looking pretty optimistic for the 18A process. However, we certainly shouldn't conclude sentiments towards Intel's process right now, given that the actual test lies in chip production, and how yield rates turn out for Team Blue, since that would most likely be decisive.
TSMC too has detailed its N2 process, revealing a 12% improvement in SRAM density due to integration of GAA technology, with high-performance SRAM seeing a phenomenal 18% improvement. The main improvement with N2 is the transition from traditional FinFET technology to a dedicated N2 "nanosheet," which has brought in a lot more process customization, along with a more precise control compared to FinFET implementation.
TSMC-Intel semiconductor race is pretty much on, and it looks like the competition is going to get a lot more fiercer, but yet again, the important factor is how the processes will turn out once they enter the supply chain.
About the author: Muhammad Zuhair is a hardware and technology reporter for Wccftech, specializing in the semiconductor industry and the complex interplay between technology, manufacturing, and geopolitics. His coverage focuses on the corporate strategies and technological roadmaps of industry giants like TSMC, NVIDIA, Samsung, and Intel. Zuhair's expertise lies in deconstructing complex topics such as fabrication nodes (e.g., 2nm process), the economic impact of policies like the CHIPS Act, and the strategic development of AI infrastructure from NVIDIA, AMD and Intel.
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