TSMC has revealed additional details about its "2nm N2" technology, disclosing massive advancements in yield rates and performance metrics.
TSMC's "N2 Nanosheet" Implementation Has Brought A Huge Rise In Node Performance, Showing Immense Potential
The Taiwan giant's 2nm process is one of the most anticipated developments in the market, mainly since the node is expected to bring in gigantic leaps in performance and efficiency results. The process is likely to come under mass production by H2 2025, and we now have information about the performance of 2nm when stacked against previous-gen counterparts, credit to the Taiwan giant's briefing at the IEEE International Electron Device Meeting (IEDM) in San Francisco, where 2nm "nanosheets" were the highlight of the briefing.
TSMC highlights that its 2nm process has witnessed 15% higher performance, with up to 30 percent less power consumption, bringing in a significant rise in node efficiency. Moreover, the process has seen a 1.15-times rise in transistor density, credited to the use of all-around gate (GAA) nanosheet transistors and the N2 NanoFlex, which allows manufacturers to squeeze in different logic cells in a minimum area, optimizing the node's performance.
By transitioning from traditional FinFET technology to a dedicated N2 "nanosheet," TSMC has managed to bring greater control over the flow of current, which allows manufacturers to fine-tune parameters depending upon process use cases. This is possible simply because nanosheets have a stack of narrow silicon ribbons, each surrounded by a gate; this ultimately allows more precise control compared to FinFET implementation.
TSMC's N2, by employing such methods, has brought a modest rise in capabilities, especially when you compare it up against 3nm and its derivatives. This is why the 2nm process is said to witness massive adoption from industry giants such as Apple and NVIDIA, given the process's generational improvements. However, with such upgrades, TSMC's N2 process will also see a parallel rise in wafer prices, with cost soaring by more than 10% compared to 3nm.
It is said that an N2 wafer could range around $25,000-$30,000 per piece, depending upon how TSMC adjusts it, but this is a giant rise compared to 3nm, which is said to be around $20,000. Not to mention that when you factor in initial yield rates and trial production, the end-production would be a lot more confined, meaning that the adoption from the process will be slower at the start.
About the author: Muhammad Zuhair is a hardware and technology reporter for Wccftech, specializing in the semiconductor industry and the complex interplay between technology, manufacturing, and geopolitics. His coverage focuses on the corporate strategies and technological roadmaps of industry giants like TSMC, NVIDIA, Samsung, and Intel. Zuhair's expertise lies in deconstructing complex topics such as fabrication nodes (e.g., 2nm process), the economic impact of policies like the CHIPS Act, and the strategic development of AI infrastructure from NVIDIA, AMD and Intel.
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