Paul McLellan talked recently to Marc Greenberg, one of Cadence's experts on the memory market. Despite the fact that the JEDEC DDR5 standard is still under development, Marc says that 2020 will be the year of DDR5. He is excited about it since a new DRAM only comes around every 8-10 years.
Cadence Outlies Its Plan To Ship Next-Gen DRAM Within 2020 Even Without The JEDEC Standard Being Formulated
This is another first in terms of DDR IP, featuring the world's first DDR5 7nm silicon IP, the world's first GDDR6 7nm silicon IP, and the world's first LPDDR5 7nm silicon IP. He was asked how we could create test chips when the standard is not even out:
Close participation in the JEDEC working groups is an advantage. We get insight into how the standard will develop. We are a controller and PHY vendor and can anticipate any potential changes on the way to final standardization. In the early days of the standardization, we were able to adopt standard elements under development and work together with our partners to get very early working silicon. As we approach the release of the standard, we get more proof points to indicate that our IP will support DDR5 devices compliant to the standard.
Marc also told said 'this is the year for shipping." Cadence already has over a dozen design-ins. He expects to see a ramp of DDR5, driven by actual servers shipping with DDR5 inside. The value proposition, especially early on, is most attractive to enterprise, cloud, big data applications. In these initial shipments, 4800 will be the speed, which is just one-speed bin above that early experiment with Micron that I linked to above. Eventually, the speeds will go higher, but 4800 will be the introductory speed. The chart above shows the switch from one DDR technology to the next. Note the red line that shows mobile DRAM, which is growing to be half the entire market for DRAM.
When it comes to platforms, AMD's 3rd Gen EPYC Genoa and Intel's Sapphire Rapids Xeon server processors are confirmed to feature support for DDR5 memory. It is unclear as to when we will see the arrival of the new memory standard on consumer platforms but with AMD introducing its Zen 4 processors in 2021 and Intel introducing its next-gen Alder lake CPUs, it is likely that we might get to see DDR5 in action on consumer-side by late 2021 or early 2022.
DDR5 Starts At 16 GB Capacities, Expected To Go Up To 24GB And 32GB
As Marc told Paul McLellan
DDR4 went to 3200 just this year. Adoption of DDR speed grades happens quite slowly. DDR5 is the next step. It is a big leap in bit rate performance. But it will then hang there for 12-18 months, then go up to 5200, and 5600 after that. We are back on the treadmill of one speed grade every 12-18 months.
In fact, the goals of DDR5 are larger dies while managing timing challenges, solve retention time problem (with on-die ECC), same speed DRAM core with a higher speed I/O, and increase one-speed grade every 12-18 months. Marc emphasized the DDR5 is more about density than speed. Using DDR5 it should be possible to have 512GB memory per channel for large dataset computing. When DDR4 was introduced, 16Gb die was impossible— now it is merely challenging. That is the entry capacity for DDR5, but it is expected to go to 24Gb and eventually 32Gb.
DDR5 is also quite well suited to stacking, so we can expect to see stacked devices allowing for even further capacity expansion. One is 3D, the other is LRDIMM technology, which allows for increased capacity. LRDIMM (LR stands for "load reduction") is a tiny sliver of the market, but it may be important for some system designers. He even mentioned up to 512GB on a single die, making it possible for a 4TB machine.