AMD Fully Discloses Zeppelin SOC Architecture Details at ISSCC 2018 – 7nm EPYC “Rome” Chips Rumored To Feature Up To 64 Cores
AMD has officially presented the latest details for their Zeppelin SOC for multi-chip architectures. The Zeppelin SOC is the codename for the die that is used on the entire range of AMD 14nm chips including Ryzen, Ryzen Threadripper and EPYC families. AMD has provided a deep dive on their grand architecture which disrupted the market upon its release in both desktop, HEDT and server segments.
AMD Details Zeppelin SOC For Multi-Chip Architectures – One SOC For Mainstream Desktop, High-End Desktop and Performance Server Markets
The AMD Zeppelin SOC was designed to cater to several market segments while being performance and power efficient. We all know that those goals were achieved spectacularly and has brought the company (AMD) back to the fight in the CPU market against Intel.
We came to know that each Zeppelin die was made up of two Core Complexes. A core complex was the building block of the Zeppelin die and included four Zen cores and their associated L2 / L3 cache. There are three products that feature the Zeppelin die, these include:
- 4-die multi-chip module (MCM) for Server
- 2-die multi-chip module (MCM) for High-End Desktop
- 1-die multi-chip module (MCM) for Desktop
Each Zeppelin die is made up of 8 Zen x86 cores and all of the products released to date are based on the first generation Zen core architecture which uses the 14nm process node. The cores have access to 4 MB of L2 cache and 16 MB of L3 cache in total. For the memory side, each Zeppelin die can deliver 2 channel DDR4 (with ECC) support allowing 2 DIMMs per channel for a maximum of 256 GB capacity per channel (EPYC).
Within each die consists a large interconnect network made up by the Infinity Fabric and Coherent connect links. Each Zeppelin die offers 32 high-speed I/O lanes which for Threadripper are 64 PCIe in total and for EPYC that’s 128 PCIe lanes.
MCM Approach versus Single-Chip Design – Cost Savings, Higher Yields, Less Problematic Production
AMD also wants to showcase the advantages of producing a MCM chip versus a single monolithic chip. Of course, Intel already released a statement calling AMD’s approach nothing more than a 4 dies glued together architecture, but EPYC has proved its worth over the Xeon lineup in both price to performance ratio and also the enhanced security and platform features that the AMD CPUs have to offer.
AMD mentions that their 4-die MCM package spans a silicon area of 852mm2, that includes the four 213mm2 Zeppelin dies. A single chip design would span an area of roughly 777mm2 and while it does offer 10% area savings, that’s touching the near reticle size limit of the manufacturing node hence increasing the manufacturing cost by 40%. A theoretical 32 core single-die design would have a 17% lower yield at a 70% higher cost.
The EPYC and Threadripper MCM solution comes with 4094 LGA pins and the entire silicon is made up of 534 Infinity Fabric high-speed chip-to-chip networks, offering up to 256 GB/s total in-package bandwidth. This is in addition to the 1760 high-speed pins which offer over 450 GB/s off-package bandwidth. The larger substrate size also yields better power delivery and management by having up to 300 Amps of current and up to 200W TDP support. You can check out more detailed info in the slides below:
AMD ISSCC 2018 Presentation (Complete)
AMD 7nm EPYC “Rome” Rumor – Two Different Dies, Up To 64 Cores Could Be Possible
Now on to some interesting bits straight from the rumor mill in China. There are reports about the AMD 7nm EPYC family. Codenamed “Rome”, the upcoming generation of EPYC processors could have up to 64 cores and 128 threads if rumors are to be believed. The rumor alleges that AMD’s 7 nm EPYC chip will actually be based on two different dies.
- Die1: Single CCX 6 core, each Die 12 core, single CPU maximum 48 core
- Die2: Single CCX 8 core, each Die 16 core, single CPU maximum 64 core
The first die will include six Zen 2 cores per core complex making up for 12 cores per Zeppelin die. Considering AMD is using the same LGA 4094 socket in the long term for Threadripper and EPYC, we can see a maximum of 48 cores and 96 threads from this die. The rumor is that there will be a second die for 7nm EPYC which will consist of 8 cores per core complex. This will allow for 16 cores off a single Zeppelin die, granting 7nm EPYC upto 64 cores and 128 threads. There’s no official word on this yet, but AMD could really disrupt the Intel Xeon market with such an outstanding core count. We will make sure to dig up more on this in future reports.