AMD Zen 3 Based EPYC Milan CPUs Up To 20% Faster Than Zen 2 Based EPYC Rome, Larger Cache & Faster Clocks
New details regarding the performance of AMD's next-generation Zen 3 based EPYC Milan CPUs have been unearthed by Hardwareluxx. The information comes from internal AMD slides which were obtained by the publication and reveal the performance potential of AMD's next-gen server powerhouse.
AMD Zen 3 EPYC Milan CPUs Up To 20% Faster Than Zen 2 EPYC Rome, Larger Cache & Faster Clocked Variants Detailed
AMD's Zen 3 based EPYC Milan CPUs are planned to ship later this year and is expected to continue performance leadership in the server segment. Based on the leaked information, AMD is definitely going to deliver another major breakthrough in server performance with its 3rd Gen EPYC family of processors.
AMD EPYC Milan Features Max of 64 Cores But Up To 20% Faster Performance
According to the report, the AMD Zen 3 core architecture has increased the IPC performance by 15 percent. However, there is a certain range of SKUs within the EPYC Milan lineup that would deliver even higher performance. AMD is taking a different approach with EPYC Milan CPUs, segmenting the 64 core for compute-intensive workloads and 32 core parts maximizing the clock-throughput.
The 64 core parts are expected to deliver a performance jump of around 10 to 15% over existing EPYC Rome 64 core processors. The 32 core parts, on the other hand, are expected to deliver a 20% performance boost over the existing 32 core EPYC Rome parts. The leak states that AMD's 32 core parts and below can achieve significantly higher clock rates than the 64 core parts. The fewer cores will be able to offer higher and more stable clock speeds than the higher core parts, hence leading to a bigger performance jump over their predecessors.
AMD's EPYC Milan CPUs will stick to a maximum of 64 cores which will be composed of 8 chiplets. These CCD chiplets will feature 8 Zen 3 cores but unlike the previous generation parts, the CCX is entirely excluded from the architecture. The CCD is a singular unit that consists of 32 MB of L3 cache shared by all 8 cores while each core has its own separate 1 MB L2 cache.
While the EPYC Milan 64 core processors feature 8 chiplets, the 32 core parts will be composed of four chiplets. That could change if AMD wants to offer 32 core parts with higher L3 cache and that would only be possible with more than 4 chiplets. We have recently seen leaked ES samples with a rated boost clock of up to 3.0 GHz in A0 revision.
AMD CPU Roadmap (2018-2020)
|Ryzen Family||Ryzen 1000 Series||Ryzen 2000 Series||Ryzen 3000 Series||Ryzen 4000 Series||Ryzen 5000 Series||Ryzen 6000 Series|
|Architecture||Zen (1)||Zen (1) / Zen+||Zen (2) / Zen+||Zen (3) / Zen 2||Zen (3)+ / Zen 3?||Zen (4) / Zen 3?|
|Process Node||14nm||14nm / 12nm||7nm||7nm+ / 7nm||7nm+ / 7nm||5nm / 7nm+|
|Server||EPYC 'Naples'||EPYC 'Naples'||EPYC 'Rome'||EPYC 'Milan'||EPYC 'Milan'||EPYC 'Genoa'|
|Max Server Cores / Threads||32/64||32/64||64/128||64/128||TBD||TBD|
|High End Desktop||Ryzen Threadripper 1000 Series (White Haven)||Ryzen Threadripper 2000 Series (Coflax)||Ryzen Threadripper 3000 Series (Castle Peak)||Ryzen Threadripper 4000 Series (Genesis Peak)||Ryzen Threadripper 5000 Series||Ryzen Threadripper 6000 Series|
|Max HEDT Cores / Threads||16/32||32/64||64/128||64/128?||TBD||TBD|
|Mainstream Desktop||Ryzen 1000 Series (Summit Ridge)||Ryzen 2000 Series (Pinnacle Ridge)||Ryzen 3000 Series (Matisse)||Ryzen 4000 Series (Vermeer)||Ryzen 5000 Series (Warhol)||Ryzen 6000 Series (Raphael)|
|Max Mainstream Cores / Threads||8/16||8/16||16/32||16/32||TBD||TBD|
|Budget APU||N/A||Ryzen 2000 Series (Raven Ridge)||Ryzen 3000 Series (Picasso Zen+)||Ryzen 4000 Series (Renoir Zen 2)||Ryzen 5000 Series (Cezanne Zen 3)||Ryzen 5000 Series (Rembrandt Zen 3)|
AMD EPYC Genoa With Zen 4 Cores To Break The 64-Core Barrier - SP5 Platform With DDR5, PCIe 5.0 & Up To 240W SKUs
The AMD EPYC Genoa processors based on the Zen 4 core architecture were a mystery until AMD officially unveiled them in their latest roadmap during the EPYC Rome launch. Currently in-design with a planned launch by 2022, the Genoa lineup would bring a brand new set of features to the server landscape.
AMD announced that EPYC Genoa would be compatible with the new SP5 platform which brings a new socket so SP3 compatibility would exist up till EPYC Milan. The EPYC Genoa processors would also feature support for new memory and new capabilities. It looks like AMD would definitely be jumping on board the DDR5 bandwagon in 2021. Since DDR5 comes with Zen 4, it is possible that AMD's Ryzen and Threadripper lines would also feature support for the new memory interface. It is also stated that new capabilities would be introduced on EPYC Genoa which sounds like a hint at the new PCIe 5.0 protocol which would double the bandwidth of PCIe 4.0, offering 128 Gbps link speeds across an x16 interface.
As per the new details, AMD's EPYC Genoa processors will feature more than 64 cores & will retain SMT2. Aside from DDR5 memory support, the leaked roadmap also mentions support for the latest Persistent Memory (NVDIMM-P) on the SP5 platform. The thermal design for Genoa will look a lot similar to existing parts with SKUs ranging from 120-240W with a few special variants featuring 225 Watt figures. It is also stated that Genoa's successor is expected to be unveiled by the second half of 2021 and we can expect the first tape out of next-generation EPYC soon.
Summing everything up for EPYC Genoa, we are looking at the following main features:
- 5nm Zen 4 cores
- SP5 Platform With New Socket
- PCIe 5.0 Support
- DDR5 Memory Support
- Launch by 2022
Genoa CPUs would be featured in the El Capitan supercomputer which is expected to deliver over 2 Exaflops of Compute power when it becomes operational in 2023. It would also utilize the next-generation CDNA2 GPUs which are solely designed for HPC workloads. The new EPYC lineup would be outfitted with the 3rd Generation Infinity Fabric architecture which you can find more details on over here.
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