AMD Unveils “EPYC” CPUs Featuring Up To 32 Cores & 64 Threads For The Datacenter
AMD has just announced its next generation CPUs for the datacenter called “EPYC” set to launch later this quarter. EPYC processors are based on AMD’s Naples CPU silicon featuring up to 32 cores, 64 threads, massive amounts of cache and I/O bandwidth.
AMD “EPYC” CPUs Designed For The Datacenter
EPYC is AMD’s reborn Opteron, a product designed to finally challenge Intel in servers. These brand new enterprise chips are built on the same 14nm FinFET manufacturing process that Ryzen processors are built on and are based on the very same Zen microarchitecture. With “EPYC” AMD states that it offers 45% more cores, 122% more bandwidth and 60% greater I/O bandwidth versus the competition. The robust feature set, in combination with Zen’s incredible power efficiency, make for a very potent server product.
|WCCFtech||AMD EPYC||AMD Ryzen|
|L1 Instruction Cache||32 KB x 32||32 KB x 8|
|L1 Data Cache||64 KB x 32||64 KB x 8|
|L2 Cache||512 KB x 32||512 KB x 8|
|L3 Cache||16 MB x 4||16 MB|
|Base Clock||TBA||Up To 3.6 GHz|
|Turbo Clock||TBA||Up To 4.0 GHz|
- A highly scalable, 32-core System on Chip (SoC) design, with support for two high-performance threads per core
- Industry-leading memory bandwidth, with 8-channels of memory per “Naples” device. In a 2-socket server, support for up to 32 DIMMS of DDR4 on 16 memory channels, delivering up to 4 terabytes of total memory capacity.
- The processor is a complete SoC with fully integrated, high-speed I/O supporting 128 lanes of PCIe 3, negating the need for a separate chipset
- A highly-optimized cache structure for high-performance, energy efficient compute
- AMD Infinity Fabric coherent interconnect for two “Naples” CPUs in a 2-socket system
- Dedicated security hardware