AMD has officially unveiled its first server product to ship with 3D V-Cache technology, the 3rd Gen EPYC Milan-X. The next-generation Zen 3 CPUs retain the outstanding Zen 3 core architecture and further enhance performance in a variety of compute-intensive workloads through increase cache.
AMD Unveils Milan-X: Featuring Zen 3 Cores With Enhanced 3D V-Cache Stack Design For Up To 804 MB Cache Per Chip
The AMD EPYC Milan-X lineup is no mystery, we already saw the chips listed at several retailers & preliminary specifications were listed too. Now we know the exact core clocks and the amount of cache that the new Zen 3 chips with 3D V-Cache vertical chiplets stacking technology will offer for server customers.
AMD EPYC Milan-X server CPU lineup will consist of four processors. The EPYC 7773X features 64 cores and 128 threads, the EPYC 7573X features 32 cores and 128 threads, the EPYC 7473X features 24 cores and 48 threads while the EPYC 7373X features 16 cores and 32 threads. The models along with their OPN codes are:
- EPYC 7773X 64 Core (100-000000504)
- EPYC 7573X 32 Core (100-000000506)
- EPYC 7473X 24 Core (100-000000507)
- EPYC 7373X 16 Core (100-000000508)
The flagship AMD EPYC 7773X will rock 64 cores, 128 threads and feature a maximum TDP of 280W. The clock speeds will be maintained at 2.2 GHz base and 3.5 GHz boost while the cache amount will drive up to an insane 768 MB. This includes the standard 256 MB of L3 cache that the chip features so essentially, we are looking at 512 MB coming from the stacked L3 SRAM which means that each Zen 3 CCD will feature 64 MB of L3 cache. That's an insane 3x increase over the existing EPYC Milan CPUs.
The second model is the EPYC 7573X which features 32 cores and 64 threads with a 280W TDP. The base clock is maintained at 2.8 GHz and the boost clock is rated at up to 3.6 GHz. The total cache is 768 MB for this SKU too. Now interestingly, you don't need to have 8 CCDs to reach 32 cores as that can be achieved with a 4 CCD SKU too but considering that you'd need double the amount of stack cache to reach 768 MB, that doesn't look like a very economical option for AMD and hence, even the lower-core count SKUs might be featuring the full 8-CCD chips.
With that said, we have the EPYC 7473X which is a 24 core and 48 thread variant with a 2.8 GHz base and 3.7 GHz boost clock and a TDP of 240W while the 16 core and 32 thread EPYC 7373X is configured at a 240W TDP with a base clock of 3.05 GHz and 3.8 GHz boost clock and 768 MB of cache.
AMD EPYC Milan-X 7003X Server CPU (Preliminary) Specs:
|CPU Name||Cores / Threads||Base Clock||Boost Clock||LLC (3D SRAM)||L3 Cache (V-Cache + L3 Cache)||L2 Cache||TDP||Price (ShopBLT)||Price (MSRP)|
|AMD EPYC 7773X||64 / 128||2.2 GHz||3.500 GHz||Yes (64 MB per CCD)||512 + 256 MB||32 MB||280W (cTDP 225W Down / 280W Up)||$9609.36 US||$8800 US|
|AMD EPYC 7763||64 / 128||2.45 GHz||3.500 GHz||N/A||256 MB||32 MB||280W (cTDP 225W Down / 280W Up)||$8616.41 US||$7890 US|
|AMD EPYC 7573X||32 / 64||2.80 GHz||3.600 GHz||Yes (64 MB per CCD)||512 + 256 MB||32 MB||280W (cTDP 225W Down / 280W Up)||$6107.88 US||$5590 US|
|AMD EPYC 75F3||32 / 64||2.95GHz||4.000 GHz||N/A||256 MB||32 MB||225W (cTDP 225W Down / 240W Up)||$5312.39 US||$4860 US|
|AMD EPYC 7473X||24 / 48||2.80 GHz||3.700 GHz||Yes (64 MB per CCD)||512 + 256 MB||12 MB||240W (cTDP 190W Down / 250W Up)||$4290.23 US||$3900 US|
|AMD EPYC 74F3||24 / 48||3.20 GHz||4.000 GHz||N/A||128 MB||12 MB||200W (cTDP 165W Down / 200W Up)||$3197.87 US||$2900 US|
|AMD EPYC 7373X||16 / 32||3.05 GHz||3.800 GHz||Yes (64 MB per CCD)||512 + 256 MB||8 MB||240W (cTDP 190W Down / 250W Up)||$5137.38 US||$4185 US|
|AMD EPYC 73F3||16 / 32||3.50 GHz||4.000 GHz||N/A||128 MB||8 MB||190W (cTDP 165W Down / 200W Up)||$3874.10 US||$1565 US|
A single 3D V-Cache stack would incorporate 64 MB of L3 cache that sits on top of the TSV's already featured on existing Zen 3 CCD's. The cache will add upon the existing 32 MB of L3 cache for a total of 96 MB per CCD. AMD also stated that the V-Cache stack can go up to 8-hi which means a single CCD can technically offer up to 512 MB of L3 cache in addition to the 32 MB cache per Zen 3 CCD. So with a 64 MB of L3 cache, you can technically get up to 768 MB of L3 cache (8 3D V-Cache CCD stacks = 512 MB) which will be a mammoth increase in cache size.
3D V-Cache could just be one aspect of the EPYC Milan-X lineup. AMD might introduce faster clocks as 7nm continues to mature and we can see much faster performance from these stacked chips. As for performance, AMD showcased a 66% performance uplift in RTL verifications with Milan-X versus the standard Milan CPU. A live demo showcased how Synopsys VCS Functional verification test was completed by Milan-X 16-core SKU much faster than the non-X 16 core SKU.
Some of the highlighted features of the AMD EPYC Milan-X lineup include:
- 3rd Gen EPYC with AMD 3D V-Cache will offer the same capabilities and features as the 3rd Gen EPYC processors and they will be drop-in compatible with a BIOS upgrade, delivering easy adoption and performance enhancements.
- Microsoft Azure HPC virtual machines featuring 3rd Gen EPYC with AMD 3D V-Cache are available today in Private Preview, with a broad rollout in the coming weeks. More information on performance and availability is available here.
- 3rd Gen EPYC CPUs with AMD 3D V-Cache will launch in Q1 2022. Partners including Cisco, Dell Technologies, Lenovo, HPE, and Supermicro are planning to offer server solutions with these processors.
AMD has announced that Milan-X will have broad platform availability through their partners such as CISCO, DELL, HPE, Lenovo, and Supermicro while the launch is planned for Q1 of 2022.
AMD EPYC CPU Families:
|Family Name||AMD EPYC Venice||AMD EPYC Turin||AMD EPYC Siena||AMD EPYC Bergamo||AMD EPYC Genoa-X||AMD EPYC Genoa||AMD EPYC Milan-X||AMD EPYC Milan||AMD EPYC Rome||AMD EPYC Naples|
|Family Branding||EPYC 7007?||EPYC 7006?||EPYC 7004?||EPYC 7005?||EPYC 7004?||EPYC 7004?||EPYC 7003X?||EPYC 7003||EPYC 7002||EPYC 7001|
|CPU Architecture||Zen 6?||Zen 5||Zen 4||Zen 4C||Zen 4 V-Cache||Zen 4||Zen 3||Zen 3||Zen 2||Zen 1|
|Process Node||TBD||3nm TSMC?||5nm TSMC||5nm TSMC||5nm TSMC||5nm TSMC||7nm TSMC||7nm TSMC||7nm TSMC||14nm GloFo|
|Platform Name||TBD||SP5 / SP6||SP6||SP5||SP5||SP5||SP3||SP3||SP3||SP3|
|Socket||TBD||LGA 6096 (SP5)|
LGA XXXX (SP6)
|LGA 4844||LGA 6096||LGA 6096||LGA 6096||LGA 4094||LGA 4094||LGA 4094||LGA 4094|
|Max Core Count||384?||256||64||128||96||96||64||64||64||32|
|Max Thread Count||768?||512||128||256||192||192||128||128||128||64|
|Max L3 Cache||TBD||TBD||256 MB?||TBD||1152 MB?||384 MB?||768 MB?||256 MB||256 MB||64 MB|
|Chiplet Design||TBD||TBD||8 CCD's (1CCX per CCD) + 1 IOD||12 CCD's (1 CCX per CCD) + 1 IOD||12 CCD's (1 CCX per CCD) + 1 IOD||12 CCD's (1 CCX per CCD) + 1 IOD||8 CCD's with 3D V-Cache (1 CCX per CCD) + 1 IOD||8 CCD's (1 CCX per CCD) + 1 IOD||8 CCD's (2 CCX's per CCD) + 1 IOD||4 CCD's (2 CCX's per CCD)|
|Memory Channels||TBD||12 Channel (SP5)|
|6-Channel||12 Channel||12 Channel||12 Channel||8 Channel||8 Channel||8 Channel||8 Channel|
|PCIe Gen Support||TBD||TBD||96 Gen 5||160 Gen 5||160 Gen 5||160 Gen 5||128 Gen 4||128 Gen 4||128 Gen 4||64 Gen 3|
|TDP Range||TBD||480W (cTDP 600W)||70-225W||320W (cTDP 400W)||200W (cTDP 400W)||200W (cTDP 400W)||280W||280W||280W||200W|