AMD CEO Shows Off Worlds First 2nm Chips For Next-Gen Helios AI Rack: Venice “Zen 6” CPU & Instinct MI455X GPU

Hassan Mujtaba
An AMD EPYC processor is displayed next to a server rack.

AMD has shown off its next-gen and the world's first 2nm EPYC Venice "Zen 6" CPU & Instinct MI455X, designed for Helios AI Racks.

AMD Dives Into The 2nm Era With Next-Gen EPYC Venice "Zen 6" CPU & Instinct MI455X GPU, Built For Helios AI Rack

AMD has finally shown off the world's first 2nm chips, which will power its next-generation AI capabilities on the Helios AI Rack. The Helios AI rack was first unveiled at the most recent Financial Analyst Day 2025, and the company promised some big performance figures with class-leading numbers and efficiency for AI workloads.

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The Helios rack is a fully liquid-cooled design that features four Instinct MI455X GPUs and a single EPYC Venice "Zen 6" CPU. The system leverages AMD's Pensando "Salina" 400 DPU, & the Pensando "Vulcano" 800 AI NIC for networking and interconnection.

Each AMD EPYC Venice "Zen 6" CPU comes with up to 256 cores based on the Zen 6C architecture, and each Instinct MI455X GPU packs several thousand compute units. The Helios rack scales up to 2.9 Exaflops of AI compute, 31 TB of HBM4 memory, 43 TB/s of scale-out bandwidth, and up to 4600 CPU + 18,000 GPU cores.

Besides the rack and tray details, AMD CEO, Dr. Lisa Su, held the company's and the world's first 2nm chips. The MI455X GPU comes with two massive GCD (Graphics Compute Dies), two MCD (Memory Controller Dies), and a total of 16 HBM4 sites. The chip is as massive as it gets.

As per previous information, the MI450X AI accelerators will feature 40 PFLOPs of FP4, 20 PFLOPs of FP8 compute performance, 432 GB of HBM4 memory with up to 19.6 TB/s bandwidth per chip, 3.6 TB/s scale-up, and 300 GB/s scale-out bandwidth. AMD has positioned its Instinct MI400 GPUs against NVIDIA's Vera Rubin, and the high-level comparison looks something like the following:

  • 1.5x Scale-Out Bandwidth vs Competition
  • 1.5x Memory Capacity vs Competition
  • Same Memory Bandwidth vs Competition
  • Same FP4 / FP8 FLOPs vs Competition
  • Same Scale-Up Bandwidth vs Competition

The other chip is the EPYC Venice "Zen 6" CPU, now packing 8 massive Zen 6C CCDs and two IODs, along with smaller chiplets with management controllers. The company has promised over 70% performance & efficiency improvement with its EPYC Venice CPUs, with a >30% increase in thread density. The chip will also come in standard 192-core "Zen 6" flavors, packing 16 CCDs, each with 12 Zen 6 cores, and 768 MB of L3 cache.

AMD is also prepping a full portfolio of data center solutions based on its EPYC Venice, MI400, & Vulcano interconnect. The solutions include a 72 GPU Rack for Hyperscale AI, an 8 GPU Enterprise AI solution with Instinct MI440X GPUs, and for Hybrid Compute, AMD is confirming its EPYC Venice-X CPUs with updated 3D V-Cache and MI430X (FP64-optimized GPUs).

AMD's 2nm chips for AI are now in production and expected to ship to customers in the second half of 2026.

Hassan Mujtaba Photo

About the author: A Software Engineer by training and a PC enthusiast by passion, Hassan Mujtaba serves as Wccftech's Senior Editor for hardware section. With years of experience in the industry, he specializes in deep-dive technical analysis of next-generation CPU and GPU architectures, motherboards, and cooling solutions. His work involves not only breaking news on upcoming technologies but also extensive hands-on reviews and benchmarking.

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