AMD Next Generation Flagship ‘Fiji XT’ Could Support 2nd Generation High Bandwidth Memory

Usman Pirzada

AMd's upcoming flagship is the Fiji XT GPU and while not much is currently known about his particular product, we do know it will feature HBM memory on board. High Bandwidth Memory currently exists in the HBM1 and HBM2 form factor, with the later part offering higher bandwidth in the same density design. According to a new rumor by Fudzilla, the Fiji XT GPU will support HBM2 - but as all rumors go, take this with a grain of salt.

AMD Feature CoverNot an official AMD poster. @AMD Public Domain

2nd Generation HBM to allegedly be featured on Fiji XT AMD GPU

The second generation HBM2 is basically 2.5D stacked DRAM via an interposer. However, it provides more throughput than HBM1 - double that of HBM1 to be exact. While HBM1 can push 128 Gigabytes per second per pin, HBM2 can push 256 Gigabytes per second per pin. That is a pretty significant difference. Now here is where the rumor gets interesting, apparently Fiji XT will not support HBM2 'out of the box', rather it will be be designed to be able to do so at at a later date - probably when HBM2 becomes mainstream.

The report also recalls a previous rumor that the Fiji XT GPU could also appear as a dual GPU on a single PCB, which would benefit immensely from HBM2. Naturally, since Nvidia has already rolled out its flagship Maxwell card a while back, the only thing that remains now is for AMD to make its move. Since they are going to be waiting till June in all likelihood, Fiji not only has to compete with Maxwell but a potential Pascal near the end of the year as well.

As far as the specifications of the high bandwidth memory standard goes, they are as follows:

4-HI HBM1 features a 1024-bit interface, two prefetch operations per IO (dual command) and can push 128GB per second per pin. The tRC is 48nm, tCCD is 2ns (1tCK), and VDD is 1.2V.  The 4-Hi HBM2 (courtesy Fudzilla) features a 1024 bit interface, two prefetch operations per IO (dual command), 64 Byte access granularity (=I/O x prefetch) and can push 256 GB per second per pin. The tRC is 48nm, tCCD is 2ns (1tCK), and VDD is 1.2V.

Basically, the next generation of graphic processors will remove bandwidth as a bottleneck and a variable to consider, mostly. While current, powerful GPU cores are usually limited to some extent by the available bandwidth, that will not be the case in the future. Although we still don't have a mainstream custom interconnect to remove the PCI-e bottleneck, in a few years or so, maybe that could change as well.

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