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AMD EPYC 7004 ‘Genoa’ CPU Engineering Sample Possibly Spotted: 32 Zen 4 Cores, Increased L2 Cache, 128 MB L3 Cache, Up To 4.6 GHz Clocks

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A possible AMD EPYC 7004 'Genoa' CPU engineering sample has been spotted within Geekebench 5 database. The sample doesn't provide us with much information if its truly a Genoa chip but there's one aspect that may confirm that it might indeed be the case.

AMD 5nm EPYC 7004 'Genoa' CPU Engineering Spotted Within Geekbench 5: Features 32 Zen 4 Cores, 32 MB L2 Cache, 128 MB L3 Cache & Up To 4.6 GHz Clocks

The leaked chip is identified as an AMD Engineering sample with the '100-000000866-01' codename and it looks very much like an upgraded version of the previous Genoa sample that leaked out back in March.

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This specific AMD EPYC Genoa chip is fabricated on the 5nm process node and will rock a total of 32 Zen 4 cores and 64 threads. In terms of clock speeds, the CPU is reported to feature a base clock of 1.20 GHz while the all-core boost is rated at 4.60 GHz.

This is an increase of 35% over the previous chip which was running at a max clock speed of 3.4 GHz. Now, these are preliminary clock speeds and we can't say for sure how well those clocks were being maintained throughout the tests. Our guess is not that good considering the lower scores compared to the 3.4 GHz sample.

AMD EPYC 7004 Genoa 32 Core engineering sample CPU has been spotted within the Geekbench benchmark database. (Image Credits: Benchleaks)

As for the cache, the L3 cache remains 32 MB per CCD and this 32 core chip packs four Zen 4 CCDs which will give 128 MB of L3 cache. The L2 cache on the other hand sees a huge bump with a 2x increase over the current Zen 3 design. The AMD EPYC Genoa CPU packs 1 MB of L2 cache per core so that's 32 MB of L2 cache on the chip whereas a 32 core variant within the Zen 3 lineup would feature only 16 MB of L2 cache. Do note that this is only a four-chiplet chip whereas the flagship Genoa chips will carry as many as 12 chiplets for a total of 96 MB L2 cache.

The platform featured 384 GB of memory which should be DDR5 since Genoa rocks a DDR5 IMC rather than DDR4 on existing Zen 3 EPYC CPUs. The Pegatron platform it was tested on featured NVIDIA's A100 80 GB PCIe accelerators. The AMD EPYC Genoa CPUs based on the 5nm process node will be offering up to 96 cores when they land on the new SP5 platform later this year. We are expecting some huge improvement in both single and multi-core performance and this leak is evident of that.

AMD EPYC CPU Families:

Family NameAMD EPYC NaplesAMD EPYC RomeAMD EPYC MilanAMD EPYC Milan-XAMD EPYC GenoaAMD EPYC BergamoAMD EPYC TurinAMD EPYC Venice
Family BrandingEPYC 7001EPYC 7002EPYC 7003EPYC 7003X?EPYC 7004?EPYC 7005?EPYC 7006?EPYC 7007?
Family Launch2017201920212022202220232024-2025?2025+
CPU ArchitectureZen 1Zen 2Zen 3Zen 3Zen 4Zen 4CZen 5Zen 6?
Process Node14nm GloFo7nm TSMC7nm TSMC7nm TSMC5nm TSMC5nm TSMC3nm TSMC?TBD
Platform NameSP3SP3SP3SP3SP5 / SP6SP5 / SP6SP5 / SP6TBD
SocketLGA 4094LGA 4094LGA 4094LGA 4094LGA 6096 (SP5)
LGA XXXX (SP6)
LGA 6096 (SP5)
LGA XXXX (SP6)
LGA 6096 (SP5)
LGA XXXX (SP6)
TBD
Max Core Count3264646496128256384?
Max Thread Count64128128128192256512768?
Max L3 Cache64 MB256 MB256 MB768 MB?384 MB?TBDTBDTBD
Chiplet Design4 CCD's (2 CCX's per CCD)8 CCD's (2 CCX's per CCD) + 1 IOD8 CCD's (1 CCX per CCD) + 1 IOD8 CCD's with 3D V-Cache (1 CCX per CCD) + 1 IOD12 CCD's (1 CCX per CCD) + 1 IOD12 CCD's (1 CCX per CCD) + 1 IODTBDTBD
Memory SupportDDR4-2666DDR4-3200DDR4-3200DDR4-3200DDR5-5200DDR5-5600?DDR5-6000?TBD
Memory Channels8 Channel8 Channel8 Channel8 Channel12 Channel (SP5)
6-Channel (SP6)
12 Channel (SP5)
6-Channel (SP6)
12 Channel (SP5)
6-Channel (SP6)
TBD
PCIe Gen Support64 Gen 3128 Gen 4128 Gen 4128 Gen 4160 Gen 5 (SP5)
96 Gen 5 (SP6)
160 Gen 5 (SP5)
96 Gen 5 (SP6)
TBDTBD
TDP Range200W280W280W280W200W (cTDP 400W) SP5
70-225W SP6
320W (cTDP 400W) SP5
70-225W SP6
480W (cTDP 600W)TBD

News Source: Benchleaks

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