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After The SP5 Socket, AMD’s EPYC Genoa CPU With 12 Next-Gen Zen 4 CCDs on 5nm Node With Up To 96 Cores Pictured

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Just a day after AMD's SP5 socket was pictured, the first picture of the EPYC Genoa CPU in its full-fat 12 Zen 4 CCD configuration has been pictured.

AMD Zen 4 Powered Full-Fat EPYC Genoa CPU Pictured: Features 12 5nm Dies For Up To 96 Cores

Discovered within the TF AMD Microelectronics publication and discovered by @phatal187, the image shows an undisclosed AMD EPYC Genoa CPU without its massive heat spreader. This chip features a total of 12 CCD's and while we don't know how many of them are enabled on this part, such configurations will offer up to 96 cores and 192 threads. There is also the massive IO die and a lot of capacitors on the interposer which will fit on the massive LGA 6096 package.

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With the recent rumors suggesting the consumer-aimed Zen 4 CPUs hitting mass production later this month, it looks like the EPYC Genoa CPUs may also be targetting mass production soon since they are planned for official launch in the second half of 2022.

Here's Everything We Know About the AMD SP5 & EPYC Genoa Server Platform!

Starting with the details, AMD has already announced that EPYC Genoa would be compatible with the new SP5 platform which brings a new socket so SP3 compatibility would exist up till EPYC Milan. The EPYC Genoa processors would also feature support for new memory and new capabilities. In the latest details, it is reported that the SP5 platform will also feature a brand new socket that will feature 6096 pins arranged in the LGA (Land Grid Array) format. This will be by far the biggest socket that AMD has ever designed with 2002 more pins than the existing LGA 4094 socket.

AMD EPYC Milan Zen 3 vs EPYC Genoa Zen 4 Size Comparisons:

CPU NameAMD EPYC MilanAMD EPYC Genoa
Process NodeTSMC 7nmTSMC 5nm
Core ArchitectureZen 3Zen 4
Zen CCD Die Size80mm272mm2
Zen IOD Die Size416mm2397mm2
Substrate (Package) AreaTBD5428mm2
Socket Area4410mm26080mm2
Socket NameLGA 4094LGA 6096
Max Socket TDP450W700W

The socket will support AMD's EPYC Genoa and future generations of EPYC chips. To get to 96 cores, AMD has to pack more cores in its EPYC Genoa CPU package. AMD is said to achieve this by incorporating a total of up to 12 CCD's in its Genoa chip. Each CCD will feature 8 cores based on the Zen 4 architecture. That aligns with the increased socket size and we could be looking at a massive CPU interposer, even larger than the existing EPYC CPUs. The CPU is said to feature TDPs of 320W which will be configurable up to 400W. You can find more details regarding the SP5 platform here.

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The physical chip is a gargantuan on its own with one of the largest CPU packages ever as pictured below:

Other than that, it is stated that AMD's EPYC Genoa CPUs will feature 128 PCIe Gen 5.0 lanes, 160 for a 2P (dual-socket) configuration. The SP5 platform will also feature DDR5-5200 memory support which is some insane improvement over the existing DDR4-3200 MHz DIMMs. But that's not all, it will also support up to 12 DDR5 memory channels and 2 DIMMs per channel which will allow up to 3 TB of system memory using 128 GB modules.

In addition to this, a  leaked AMD slide also confirms future EPYC SOCs to feature higher DDR5 pin speeds of up to 6000-6400 Mbps. This could probably be referring to Turin or Bergamo as they are the ones that succeed Genoa.

The main competitor of AMD's EPYC Genoa lineup would be Intel's Sapphire Rapids Xeon family which is expected to launch in 2022 too with PCIe Gen 5 and DDR5 memory support. The lineup was recently rumored to not get a volume ramp until 2023 which you can read more about over here. Overall, AMD's Genoa lineup seems to be in great form after this leak and could be a major disruption for the server segment if AMD plays its cards right till Genoa's launch by 2022.

AMD EPYC CPU Families:

Family NameAMD EPYC NaplesAMD EPYC RomeAMD EPYC MilanAMD EPYC Milan-XAMD EPYC GenoaAMD EPYC BergamoAMD EPYC TurinAMD EPYC Venice
Family BrandingEPYC 7001EPYC 7002EPYC 7003EPYC 7003X?EPYC 7004?EPYC 7005?EPYC 7006?EPYC 7007?
Family Launch2017201920212022202220232024-2025?2025+
CPU ArchitectureZen 1Zen 2Zen 3Zen 3Zen 4Zen 4CZen 5Zen 6?
Process Node14nm GloFo7nm TSMC7nm TSMC7nm TSMC5nm TSMC5nm TSMC3nm TSMC?TBD
Platform NameSP3SP3SP3SP3SP5 / SP6SP5 / SP6SP5 / SP6TBD
SocketLGA 4094LGA 4094LGA 4094LGA 4094LGA 6096 (SP5)
LGA XXXX (SP6)
LGA 6096 (SP5)
LGA XXXX (SP6)
LGA 6096 (SP5)
LGA XXXX (SP6)
TBD
Max Core Count3264646496128256384?
Max Thread Count64128128128192256512768?
Max L3 Cache64 MB256 MB256 MB768 MB?384 MB?TBDTBDTBD
Chiplet Design4 CCD's (2 CCX's per CCD)8 CCD's (2 CCX's per CCD) + 1 IOD8 CCD's (1 CCX per CCD) + 1 IOD8 CCD's with 3D V-Cache (1 CCX per CCD) + 1 IOD12 CCD's (1 CCX per CCD) + 1 IOD12 CCD's (1 CCX per CCD) + 1 IODTBDTBD
Memory SupportDDR4-2666DDR4-3200DDR4-3200DDR4-3200DDR5-5200DDR5-5600?DDR5-6000?TBD
Memory Channels8 Channel8 Channel8 Channel8 Channel12 Channel (SP5)
6-Channel (SP6)
12 Channel (SP5)
6-Channel (SP6)
12 Channel (SP5)
6-Channel (SP6)
TBD
PCIe Gen Support64 Gen 3128 Gen 4128 Gen 4128 Gen 4160 Gen 5 (SP5)
96 Gen 5 (SP6)
160 Gen 5 (SP5)
96 Gen 5 (SP6)
TBDTBD
TDP Range200W280W280W280W200W (cTDP 400W) SP5
70-225W SP6
320W (cTDP 400W) SP5
70-225W SP6
480W (cTDP 600W)TBD

News Source: HXL

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