Xeon Phi Coprocessor (Intel) Codenamed Knights Landing Unvieled.

Usman Pirzada
Posted Jul 24, 2013
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Knights Landing Xeon Phi

The Xeon Phi Coprocessor family took a step into the spotlight after the opening of the Tianhe-2 Supercomputer, which coupled Intel’s Xeon Processors with the Xeon Phi Coprocessors to outstanding success. Needless to say the landscape of supercomputing might be in for a change. Most Supercomputing clusters use HPC (High Performance Computing) GPGPUS (General Purpose GPUs) such as Nvidia Tesla along with processors, but the major disadvantage of the GPGPUS is that they require special code and a CPU to operate. While as the Xeon Phi Coprocessor requires neither special code nor a CPU to operate and delivers unparalleled performance.

3D Tri-gate Transistors and 512 AVX in Xeon Phi ‘Knights Landing’

The current generation of Intel’s Coprocessor Series Codenamed Knights Corner is made from a 22nm process and delivers a peak double precision performance of 1.2 Teraflops per Coprocessor. Knights Corner Coprocessors also use the newly integrated Haswell AVX2 instruction set which widens the Integer register to 256 bit. AVX is the instruction set for floating point operations. Though the Knights Corner family uses the 3D Trigate transistors their power is not truly realized yet.

Cue the Knights Landing series of Xeon Phi Coprocessors which will be constructed with a 14nm process derived from Skylake and Broadwell and will use a much widened 512 bit AVX instruction set. Intel also promises that the Knights Landing Coprocessors will break the 3 Teraflop Barrier in Double Precision performance! So we can safely assume that the Xeon Phi Coprocessors of the Knights Landing era will finally fully utilize the 3D Tri-gate technology.

Knights Landing Xeon Phi

The Future of High Performance Computing (HPC) in relation to Xeon Phi

With the current HPC and Supercluster market dominated by GPGPUS and the Xeon Phi Coprocessor still in relative infancy it is anybody’s bet on what tomorrow will look like. GPGPUs such as Nvidia Tesla run Parallelization code with an unbelievable efficiency owing to their multitude of cores and verified architecture. But one thing is clear, the GPGPU disadvantage of requiring special code and dependence on a CPU is a big one. If in the coming years the GPGPU is not able to rid itself of this, the future will belong to Coprocessors such as the Xeon Phi. With the Xeon Phi coprocessors already proving themselves at the Tianhe-2 cluster and the upcoming exponential increase in performance with the Knights Landing series, the future for Intel’s co processing venture looks very bright indeed.

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Xeon Phi Knights Landing


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