Intel Hints At New 2.5 Year ‘Tick Tock Tock’ Cadence – Confirms 14nm Kaby Lake Intermediary Platform and 10nm Cannonlake Delay to 2017

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Jul 18, 2015
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Intel recently held their earnings conference and confirmed our reports of the Cannonlake delay and the existence and arrival of Kaby Lake as an intermediary platform. That’s not it either, embedded deep within the lines of the transcript is a pretty big hint. Intel appears to be moving from a 2 year, Tick Tock Cadence to something I have unofficially dubbed the “Tick Tock Tock” (2.5 Year+) Cadence.

Related Intel Drops Tick-Tock Strategy Once and For All – Now Aims at Process, Architecture and Optimization, 3 Year Cadence

Intel expands the definition of Moore’s Law with a new 2.5 year cadence – Kaby Lake arriving in 2H 2016 and Cannonlake in 2017

Kaby Lake was originally thought to be a Skylake Refresh platform in which the current SKL architecture is revised on the 14nm Node (and slight speed bumps can be expected in the frequency of most processors). However, Intel doesn’t seem to be orienting it as a refresh platform, rather a third “product”. Even if that is true, stripping away the marketing intent and I am of the opinion that we are looking at a glorified refreshthis time with minor architectural updates and a new nomenclature.  Latest reports indicate that Kaby Lake or KBL will be arriving on September 2016 for the mainstream variants and early 2017 for the enterprise versions. The notebook lineup will however will allegedly be available by as early as January 2016.

Cannonlake on the other hand, has been delayed much further into 2017 like previously reported. This means that the 10nm platform wont be arriving till early 2017 at the earliest. The official reason, like always is poor yields and this time, I can’t really say I doubt them. It would be be exponentially hard to win a race against physics and it makes sense to milk the nodes you are able to conquer, figuratively speaking. This is also where the second part of our article comes in, but before we do that, take a look at the following para which is a direct quote from the earnings transcript:

As node transitions lengthened, we adapted our approach to the Tick-Tock method, which gave us a second product on each node. This strategy created better products for our customers and a competitive advantage for Intel. It also disproved the death of Moore’s Law predictions many times over. The last two technology transitions have signaled that our cadence today is closer to 2.5 years than two.

To address this cadence, in the second half of 2016 we plan to introduce a third 14-nanometer product, code named Kaby Lake, built on the foundations of the Skylake micro-architecture but with key performance enhancements. Then in the second half of 2017, we expect to launch our first 10-nanometer product, code named Cannonlake. We expect that this addition to the roadmap will deliver new features and improved performance and pave the way for a smooth transition to 10-nanometers.

This would be Intel’s CEO confirming the presence of a new intermediary platform and the delay of 10nm to 2017, more or less breaking the Moores Law as we know it (or redefining it if you will). One of the more interesting things however, is the fact that he more or less stated outright that Intel is going to be adding a new step in the Tick-Tock model. If the Kaby Lake platform is a reliable template then we are going to be looking at 3 products (atleast) on the 10nm process as well, just like 14nm will now have 3 processes (Broadwell, Skylake and Kabylake). I have duly christened the new model Tick Tock Tock, but ofcourse, its really upto Intel what they decide to call it.

Related Intel’s 10nm Volume Ramp and Cannonlake Microarchitecture Delayed Due to Yield Problems

Also, like I mentioned above, I find it unlikely that the third iteration in Intel’s lithographic cadence will be a significant architectural upgrade; making it a rather advanced form of a refresh. With just the addition of half a year, it would be nearly impossible to add another brand new architecture (R&D for microarchitectures is started years before!) to the mix without upsetting the perfect expense and revenue optimization.  Its also worth pointing out that Intel has previously admitted that lithography below 7nm is mostly on the drawing board at this stage. While EUV can handle 7nm just fine, Intel hasn’t even decided upon the base material to the processes below(as opposed to silicon)! Physics is finally taking its toll on the blue giant, and Moores Law is either dead or in its last reincarnation before being dropped for good.

A copy of the transcript can be found over at Seeking Alpha.

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