AMD Publishes Patent for Zen Based APUs with Integrated FPGAs and HBM2 Memory on a 2.5D Interposer
Intel has long since offered a lineup of special processors with FPGAs from Altera onboard. And if a patent that was recently published is to be believed, AMD is planning to do something similar with its future processors as well. With the major addition of having 2.5D stacked HBM2 (memory) at the same time. The target audience of these special CPUs are very specific and usually consist of sometimes semi-custom customers where the load type shifts regularly.
AMD files patent for Zen based processors with FPGAs and HBM2 onboard
FPGAs stand for Field Programmable Gate Arrays. For those not familiar with them, they are a type of processing device that has reconfigurable logic. Basically, you have ASICs which have hard-wired logic, tailored to a specific task and a specific load type allowing them to accomplish said tasks with unparalleled efficiency. Then, you have our modern day CPUs with hard-wired logic that allows many general applications and diverse load types resulting in an all rounder processor capable of doing just about everything – but not very good at certain load types. And finally, you have FPGAs, whose logic is not hard-wired and can be reconfigured accordingly resulting in a very customizable silicon solution for the semi-custom market.
The addition of HBM2 memory would enable AMD offerings to have an edge over Intel’s. While Intel is dabbling in Hybrid Memory Cubes, it has not yet, managed to integrate it into an Xeon FPGA lineup. Also if Zen micro-architecture lives up to its name, it should be more than a match for Intel’s counterparts – especially considering the main requirement for most data-centres and semi-custom servers is energy efficiency (something HBM2 will excel at, not to mention Zen). Infact AMD has already been approached by Facebook to build them a semi custom server processor for their data centres and there is a probability involved (caution: speculation) that this patent might have something to do with that.
HBM2 (memory) offers significant bandwidth upgrades over HBM1 while staying on the same VDD level of 1.2V. And with the advances made (or rather promised) in Zen micro-architecture, the power efficiency of this contraption should be pretty impressive. Unfortunately, like most patents, this one is pretty vague as well, but from what I could gather, the reconfigurable logic (FPGAs) will be an optional intermediary step between the main processor and the memory. Providing the FPGA with custom logic, will allow the user to minimize latency and drastically reduce bottlenecks of any interconnect and get workloads processed almost directly. Its also worth noting that this is almost certainly an APU design – so Greenland graphics should be on the table as well.