AMD Shifting to One Floating Point Unit Per Core Design with Upcoming Zen Processors – Dropping Shared Core Approach of Excavator
Fudzilla has been leaking streams of information about the upcoming Zen processor for quite some time now and they appear to have posted an update. As always, please start by carefully looking at the rumor tag besides the title. Our more informed readers might recall that the Excavator architecture had a shared FPU design, with one floating point unit being shared between two cores. In what appears to be a move to get back on track, the source reveals that AMD is switching back to one FPU per core design – something Intel already follows.
AMD forgoes the shared core design with Zen – adopts the traditional one FPU per one core
The shared FPU design was one of the most debated things about the architecture of previous AMD processors. Basically, whenever the FPU was in use by a core, the other core had to wait till the FPU finished its current task – acting as a bottleneck and leading to accusations of the flagship processor not being a “true” 8 core. The rationale given behind the decision was because of space problems on the die and higher integer throughput to be achieved. With the shift to sub-20m architecture however there will be ample space in the cores for an integrated FPU. You might also remember that Zen will be shifting to Simultaneous Multi Threading (SMT) approach and leaving behind CMT so every Zen core should be able to run two threads. Basically, AMD is making a comeback in Intel style, in full force.
That’s not it either, Zen will be using a scheduling model that is similar to Intel’s and it will use specific hardware and simulation to define any needed scheduling or NUMA changes. It will also be ISA compatible with Haswell/Broadwell style of compute. It will bring various compiler optimisations, including GCC with target of SPECint v6 based score at common compiler settings. Benchmarking and performance compiler LLVM targets SPECint v6 rate score at performance compiler settings. Each Zen core will have access to 512KB of L2 cache and 4 Zen cores will share 8MB of L3 cache.
All this, if true, and it does seem like the leak is authentic, indicates AMD implementing a plethora of changes in Zen based processors – something that will bring the processor closer to Intel based design and something that could only be described as very promising in nature. With all these proposed shifts in structure, AMD could actually be poised to gain IPC improvements over the current generation of Intel processors – something that hasn’t even been a possibility in a very long time. A few months ago, the design schematic of Zen based processors was posted on a forum. While its authenticity was anything but confirmed, I am now beginning to suspect it was the real deal.
The old leak showed each Zen Core adapting a very traditional CPU layout with one large integer cluster and one large floating point unit. In comparison, an excavator core diagram featured two integer clusters and one floating point unit (the 2 shared core design basically). While the old excavator design allowed the Bulldozer family of processors to achieve high performance in Integer based calculations, the floating point performance was understandably crippled. Since Zen also forgoes the double decoder style of Excavator architecture, featuring the single decoder approach, the single thread – single core performance of Zen should be significantly higher than anything we have seen from AMD before. All these seeming minor changes are shaping up to be one giant performance (and IPC ) upgrade and I for one can’t wait to test the architecture when it launches.