AMD Zen ”Quad Core Unit” Block Diagram Leaked – AMD Opteron to feature MCM Design with Eight Zen Units
Just a few hours after the first block diagram of AMD's new Zen x86 Micro-architecture was leaked, now we have a second leak direct from Planet3dnow which shows us a "Zen based Quad Core Unit" block diagram. The diagram features a single quad core unit with 4 Zen cores and will form the basis of AMD's design philosophy where Zen is involved. In the meantime, Fudzilla reports that the Opteron 32 Core processor will utilize a Multi Chip Module design with 8 cores in each die (and 4 dies).
One "Zen Unit" equals four x86 Zen Cores - Block diagram leaked
The block diagram reveals only one more fact that the previous block diagram did not: L3 Cache will be shared among 4 Zen cores. We are also looking at the basic building block of all Zen products. Since AMD uses a lego-like philosophy in designing architecture, where nearly every design is compatible with others, this "basic building block of Zen" will be featured across many products - of that I am sure. We already know for eg, that a 16 core Zen APU (with 4 Zen Units) is in the works along with a 32 Core Opteron Processor (with 8 Zen Units). AMD will be launching Opteron processors sometime in 2016 and are thought to be manufactured on the 14nm GloFo node.
We have some additional details on the 32 core Opteron processor as well. The processor has 4 dies and each die has 8 zen cores. Basically, you are looking at two Zen Units per die. Each die will have 2 memory channels and each channel will support exactly 2 DIMM slots. Thats a total of 4 DIMM slots (the standard) per 8 core die and upto 16 DIMM slots. The TDP of the Opteron Processor will be 140W but there will also be a 120W variant along with even less power hungry SKUs. AMD will also be employing 2 combo links per die which combine 8 and 16 bit links and can be in the form of xGMI, PCIe, SATA/SATA-e, 10Gbase-KR and SGMII. There will be 1P socket boards as well along with 2P socket boards configurations (thats a resounding total of 64 Zen cores per board people).
The excess silicon space that results from the removal of Greenland graphics is given to L2, L3 cache as well as its Zen x86 cores. Each core will have 512KB of L2 cache and 4 cores will share 8MB worth of L3 cache. The processor will be divided into eight clusters of 4 cores each for a net total of 32 cores. A platform security model of the same will enable security features which include secure boot and cryptographic co processing. The next generation Opteron processor has eight DDR4 memory channels capable of handling 256GB per channel. The chipset supports PCIe Gen 3 SATA, 4x10GbE Gig Ethernet and Sever controller HUB.
2P motherboard will have two sockets capable of running two Opteron processors in conjunction and will support four AMD External Global Memory interconnect xGMI links. Whereas the standard 1P configuration comes with 64 PCIe lanes per socket, 16 SATA lanes, four 10GigE and four 1GigEs. AMD will utilize coherent interconnect to bridge the two seats on the 2p boards.
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