Say Hello To GAAFET! Samsung Details Plans For 7LPP, 5LPE, 4LPE/LPP And 3GAAE/GAAP Processes
After Samsung detailed its plans for 8nm LPP last year, the Korean tech giant is ready to move forward. It’s that time of the year when Samsung lays down its current and future semiconductor plans. The Korean tech giant is feeling particularly generous this year as it provides us with details for no less than four generation of processors. These include 7nm, 5nm, 4nm, and 3nm processes. Take a look below for more details.
Samsung Lays Down Plans For Its 7LPP, 5LPE, 4LPE/LPP, And 3GAAE/GAAP Processes In Detailed Roadmap; 7LPP Will Be Ready For Production Later This Year
In the last few months of 2017, Samsung unveiled its plans for 8nm LPP (Low-Power-Plus). The process was expected as a buffer between 10LPP and 7LPP, with the latter all set as Samsung’s first processor node to utilize Extreme Ultraviolet (EUV) lithography. 8LPP uses narrower metal pitches and provides up to 10% area reduction and power efficiency when compared to the current 10LPP.
After reports that Cadence’s tools have been certified for Samsung’s 8LPP, the company is ready to provide details for its next four generations of processor nodes. Samsung has unveiled its plans at its annual US Foundry Forum, in Santa Clara. At the conference, it has revealed some impressive details.
First off, Samsung has provided more details of its plans for 7LPP. The company will be ready for production by the second half of this year and key IPs should complete development by the first half of 2019. Next up is 5LPE (Low-Power-Early), which will utilize strengths and experiences from 7LPP – Samsung’s first processor node to be manufactured with EUV.
The company will mark the conclusion of FinFET designs with 4LPP and LPE. They will adopt 5LPE structurally, as the manufacturer will interconnect its nodes. 7LPP will lead to 5LPE which in turn will result in improved scaling and smaller cell sizes with 4LPP and 4LPE.
Bidding farewell to FinFET with 4nm, Samsung will then proceed to utilize GAAFET (Gate All Around FET). Heading into 3nm, it will have plenty of experience under its belt. In June of 2017, Samsung and IBM launched the first 5nm GAAFET chip, that featured 30 Billion transistors per 50mm².
While this represents an optimal condition, it was nevertheless a huge step. It’s also interesting to note that last year, Seoul claimed that 4nm will be its first process to use GAAFET – but it has changed its plans now.
After being done with 4nm, the company will use its custom Multi-Bridge-Channel FET (MBCFET) that will be based on gate control. It’s very optimistic and honestly, we can’t wait. It’s time GAAFET is available for the masses, but this will take a while. Thoughts? Let us know what you think in the comments section below and stay tuned. We’ll keep you updated on the latest.