Samsung and SK hynix are using two different approaches to manufacture next generation DRAM memory chips, suggest industry insiders. The boom in demand for computing products ushered in by AI data center buildouts has strained the memory market led to a tightness in the markets for HBM, DRAM and other chips since all of these rely on the same raw materials for production. As part of its efforts to manufacture next generation chips, the sources suggest that Samsung is interested in using the gate-all-around FET (GAAFET) fabrication technology for its next generation DRAM chips.
Samsung Seeking To Apply NAND Manufacturing Technology To DRAM Production, Suggests Report
While the manufacturing technology processes for application processors use terms denoted by nanometers, technologies for memory chips rely on different nomenclature. Alphabet codes are used to describe a set of manufacturing nodes, with terms such as 1c describing products manufactured at the 10 nanometer node or below.
Since memory chips differ from processors by the merit of having to store data, their fabrication also includes creating a capacitor to hold the data. This capacitor works with a transistor and as node sizes decrease, the complexity of storing data inside it grows since the capacitor has to be of a certain size in order to be workable.
As a result, chip manufacturers are moving towards 3D DRAM, where transistors are laid down horizontally instead of being stacked vertically since advanced in manufacturing allow for greater density which increases the chance of two transistors coming into contact with each other.
One approach that Samsung is developing for its newer DRAM chips is using the GAAFET manufacturing process technology. In application processor fabrication, GAAFET wraps the gate of a transistor around its channel. As the gate is responsible for controlling the flow of current in a transistor, the increased contact of the gate with the channel in GAAFET leads to improved performance.
However, according to the sources, since a DRAM chip also consists of capacitors, Samsung has to integrate a GAAFET transistor and a capacitor inside a DRAM cell. One technique that the firm is considering is placing the chip's circuitry, which manages operations such as read and write, under the memory array as is the case with NAND chips.
On the flip side, SK hynix is experimenting with the 4F² approach where the transistors are stacked vertically with the gate material wrapped around them. This is similar to the GAAFET process, and the chip's components responsible for receiving data from the capacitor are placed under the transistor pillar.
According to the source, SK hynix and Samsung are racing to get their approach recognized first in order to make it the standard model and dominate the next generation of DRAM chips.
About the author: Ramish is a seasoned technology writer and editor with more than a decade of experience. He specializes in semiconductor fabrication and market analysis. With a background in finance and supply chain management - via his bachelors in Finance and a micromasters in supply chain management from MIT - Ramish combines financial rigor with deep industry insight to deliver accurate and authoritative coverage.
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