PCI-SIG has released the PCIe 8.0 specification with the 0.5 draft detailing up to 1 TB/s bandwidth & 256 GT/s data rates.
PCIe 8.0 Standard Will Be Ready by 2028, Made For Next-Gen Data Centers With 1 TB/s Bandwidth
The PCIe 8.0 specification highlights a major uplift versus existing standards, offering 8x the raw data rate and bandwidth of PCIe 5.0. On paper, PCIe 8.0 offers a 256 GT/s data rate and 1 TB/s of raw bi-directional bandwidth via a 16x lane configuration. The standard utilizes the PAM4 signaling technology and is backward-compatible with existing PCIe technology.
PCI-SIG states that they are evaluating new connector technologies with PCIe 8.0, and the standard will offer improved bandwidth through protocol enhancements while reducing power through additional techniques.
The new PCIe standard conforms to PCI-SIG's long-term roadmap, which will double the IO bandwidth every 3 years. The following is the breakdown of PCIe 8.0 bandwidth across different lane configurations:
- x1 - 64 GB/s
- x2 - 128 GB/s
- x4 - 256 GB/s
- x8 - 512 GB/s
- x16 - 1024 GB/s
At x1 mode, PCIe 8.0 will offer the same bandwidth as PCIe 4.0 at x16 mode and PCIe 5.0 at x8 mode. At x2 mode, the new standard matches the full bandwidth of PCIe 5.0, and at x4 mode, it matches the full capability of PCIe 6.0 standards.
Press Release: The PCI-SIG technical work groups are hard at work on the PCI Express (PCIe) 8.0 specification, and we are pleased to announce that draft 0.5 is now available for member review – ahead of schedule for a typical draft 0.5 release. This is the official first draft of the specification, incorporating all the feedback we received from members after the release of draft 0.3 in September 2025. With this release, the PCIe 8.0 specification remains on track for full release by 2028.
PCIe 8.0 Specification Objectives:
- Delivering 256.0 GT/s raw bit rate and up to 1.0 TB/s bi-directionally via x16 configuration
- Evaluating new connector technology
- Ensuring latency, FEC, and reliability targets are achieved
- Maintaining backwards compatibility with previous generations of PCIe technology
- Improving bandwidth through protocol enhancements
- Reducing power through additional techniques
The goal of the PCIe 8.0 specification is to deliver the high bandwidth and low latency needed for data-intensive markets, including AI, data centers, high-speed networking, Edge computing, Quantum computing, and more.
About the author: A Software Engineer by training and a PC enthusiast by passion, Hassan Mujtaba serves as Wccftech's Senior Editor for hardware section. With years of experience in the industry, he specializes in deep-dive technical analysis of next-generation CPU and GPU architectures, motherboards, and cooling solutions. His work involves not only breaking news on upcoming technologies but also extensive hands-on reviews and benchmarking.
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