SPHBM4 is a new JEDEC standard that aims to solve the high cost and packaging concerns with existing HBM technologies.
HBM Demand Keeps on Surging, But The High-Cost Might Make JEDEC's Upcoming SPHBM4 A Better Alternative
Almost all AI & HPC accelerators rolling out these days feature some form of HBM memory. The highest-end solutions are leveraging the latest HBM4 designs, and HBM4E is being sampled to the top chipmakers.
But as demand continues to rise, and shortages persist in the premium DRAM segment, HBM has become a major bottleneck. The cost is one issue, but price surges are a direct result of packaging technologies that HBM requires. As HBM evolves, more advanced packaging solutions will become a necessity.
There are several ways being discussed to circumvent these concerns with HBM, such as the HBF, ZAM, and 3D-Stacked Flash, but these have yet to see commercialization. In the meantime, JEDEC is proposing a new standard that expands the application scope of HBM. This new standard is called SPHBM4.
According to JEDEC on the 21st, the new HBM4 standard, 'SPHBM4 (Standard Package HBM4),' was finally approved by the Board of Directors following discussions by the DRAM Memory Subcommittee (JC-42.2).
SPHBM4 is a specification designed to maintain the performance of existing HBM4 while enabling use with fewer signal pins and standard packaging structures. This signifies a reduction in reliance on expensive, advanced packaging and an expansion of the application range for high-performance memory.
The idea is simple and aims to maintain the performance of existing HBM solutions, such as HBM4, while using fewer signal pins. The other part is the use of standard packaging, hence the "SP" in the name. This will enable HBM makers to reduce the reliance on expensive advanced packaging solutions.
Reduction in signal pins will lead to some performance losses, but SPHBM4 mitigates this by increasing the signal speeds fourfold while reducing the number of signal pins to 1/5th.
This leads to HBM-level bandwidth while using standard substrates. The connection between the memory and the compute die also changes to 20mm. This increased distance enables better internal thermal management for the package.
An industry insider stated, "If glass substrates serve as the foundation for implementing large packages, SPHBM4 is a standard that enables the more economical placement of HBM-class memory within them," adding, "As the adoption of SPHBM4 expands, the value of glass substrates could increase in tandem with the demand for large packages."
Some research analysts state that SPHBM4 and future standard-packaged HBM solutions have a potential for integration with glass substates. Glass Substates come with advantages over existing substrate technologies, such as higher thermal stability, flatness, and finer wiring.
The Glass Substrates are primed to become a major semiconductor focus in the coming years, with lots of work already underway, but they have yet to reach mass production. Trial production is expected in the coming years, and true commercialization is expected around 2030.
While surging demand for HBM continues to drive innovation in AI and HPC, its high cost and reliance on advanced packaging remain significant challenges. JEDEC’s newly approved SPHBM4 offers an elegant and timely solution: delivering near-HBM4 performance using fewer signal pins, standard packaging, and much more economical substrates.
By quadrupling signal speeds and enabling better thermal management, SPHBM4 lowers barriers to adoption without sacrificing meaningful bandwidth. As it pairs naturally with emerging glass substrates, this new standard could significantly broaden access to high-performance memory, easing current shortages and paving the way for more scalable, cost-effective AI systems in the years ahead.
About the author: A Software Engineer by training and a PC enthusiast by passion, Hassan Mujtaba serves as Wccftech's Senior Editor for hardware section. With years of experience in the industry, he specializes in deep-dive technical analysis of next-generation CPU and GPU architectures, motherboards, and cooling solutions. His work involves not only breaking news on upcoming technologies but also extensive hands-on reviews and benchmarking.
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