Intel 4th Gen Xeon Sapphire Rapids-SP CPUs To Feature Up To 56 Cores on 10nm Enhanced SuperFin Process & 350W TDP
Details regarding Intel's 4th Gen Xeon family codenamed Sapphire Rapids-SP have leaked out a day after the launch of the 3rd Gen Xeon family. The Sapphire Rapids-SP family will be replacing the Ice Lake-SP family and will go all on board with the 10nm Enhanced SuperFin process node that will be making its formal debut later this year in the Alder Lake consumer family.
Intel Sapphire Rapids-SP 4th Gen Xeon CPUs Detailed - 10nm Enhanced SuperFin Process Node, Up To 56 Cores & 350W TDP
Update: Videocardz has leaked a Xeon comparison chart, coming directly from Intel, which more or less confirms this information and also along with these, a few other tidbits such as the instruction sets and specific I/O capabilities of the Sapphire Rapids-SP family.
In an SKU chart posted by Momomo_US, three Intel Sapphire Rapids-SP Xeon CPUs are disclosed. All three SKUs are engineering samples and come with various core configurations. From what we know so far, Intel's Sapphire Rapids-SP lineup is expected to utilize the Golden Cove architecture & will be based on the 10nm Enhanced SuperFin process node.
The Sapphire Rapids lineup will make use of 8 channel DDR5 memory with speeds of up to 4800 MHz and support PCIe Gen 5.0 on the Eagle Stream platform. The Eagle Stream platform will also introduce the LGA 4677 socket which will be replacing the LGA 4189 socket for Intel's upcoming Cedar Island & Whitley platform which would house Cooper Lake-SP and Ice Lake-SP processors, respectively. The Intel Sapphire Rapids-SP Xeon CPUs will also come with CXL 1.1 interconnect that will mark a huge milestone for the blue team in the server segment.
— 188号 (@momomo_us) April 6, 2021
Coming to the configurations, the top part is started to feature 56 cores with a TDP of 350W. What is interesting about this configuration is that it is listed as a low-bin split variant which means that it will be using a tile or MCM design. The Sapphire Rapids-SP Xeon CPU will be composed of a 4-tile layout with each tile featuring 14 cores each. The other two parts that have been mentioned use a monolithic design. A 24 core part with 225W TDP (Lowest Volume) and a 44 core part with 270W TDP (High Volume + Speed Select) are listed too.
It looks like AMD will still hold the upper hand in the number of cores & threads offered per CPU with their Genoa chips pushing for up to 96 cores whereas Intel Xeon chips would max out at 56 cores if they don't plan on making SKUs with a higher number of tiles.
The Intel Saphhire Rapids CPUs will contain 4 HBM2 stacks with a maximum memory of 64 GB (16GB each). The total bandwidth from these stacks will be 1 TB/s. According to leaked details from AdoredTV, HBM2 and GDDR5 will be able to work together in flat, caching/2LM, and hybrid modes. The presence of memory so near to the die would do absolute wonders for certain workloads that require huge data sets and will basically act as an L4 cache.
The platform would be competing against AMD's Zen 4 based EPYC Genoa lineup which would also be moving to a newer platform known as SP5. AMD has promised new memory along with new capabilities for the Genoa lineup which would include support for 8-Channel DDR5, up to 80 PCIe 5.0 lanes, and more. The platform itself would be scalable up to 8 sockets which means that we can see core counts of up to 448 and up to 996 threads on a single server (using 56 core chips).
Currently, AMD's EPYC CPUs demolish Intel in terms of performance per watt, a number of cores/threads, feature set, and total cost of operation with major players in the server segment switching their cloud datacenters to AMD's EPYC CPUs. It remains to be seen if Intel can make a complete or even a partial recovery of its Xeon segment with Sapphire Rapids. For now, Intel is focusing on a launch for its Sapphire Rapids Xeon Scalable family in 2022 but a volume ramp is not expected until early 2022.
Intel Xeon SP Families (Preliminary):
|Family Branding||Skylake-SP||Cascade Lake-SP/AP||Cooper Lake-SP||Ice Lake-SP||Sapphire Rapids||Emerald Rapids||Granite Rapids||Diamond Rapids|
|Process Node||14nm+||14nm++||14nm++||10nm+||Intel 7||Intel 7||Intel 3||Intel 3?|
|Platform Name||Intel Purley||Intel Purley||Intel Cedar Island||Intel Whitley||Intel Eagle Stream||Intel Eagle Stream||Intel Mountain Stream|
Intel Birch Stream
|Intel Mountain Stream
Intel Birch Stream
|Core Architecture||Skylake||Cascade Lake||Cascade Lake||Sunny Cove||Golden Cove||Raptor Cove||Redwood Cove?||Lion Cove?|
|IPC Improvement (Vs Prev Gen)||10%||0%||0%||20%||19%||8%?||35%?||39%?|
|MCP (Multi-Chip Package) SKUs||No||Yes||No||No||Yes||Yes||TBD (Possibly Yes)||TBD (Possibly Yes)|
|Socket||LGA 3647||LGA 3647||LGA 4189||LGA 4189||LGA 4677||LGA 4677||TBD||TBD|
|Max Core Count||Up To 28||Up To 28||Up To 28||Up To 40||Up To 56||Up To 64?||Up To 120?||Up To 144?|
|Max Thread Count||Up To 56||Up To 56||Up To 56||Up To 80||Up To 112||Up To 128?||Up To 240?||Up To 288?|
|Max L3 Cache||38.5 MB L3||38.5 MB L3||38.5 MB L3||60 MB L3||105 MB L3||120 MB L3?||240 MB L3?||288 MB L3?|
|Memory Support||DDR4-2666 6-Channel||DDR4-2933 6-Channel||Up To 6-Channel DDR4-3200||Up To 8-Channel DDR4-3200||Up To 8-Channel DDR5-4800||Up To 8-Channel DDR5-5600?||Up To 12-Channel DDR5-6400?||Up To 12-Channel DDR6-7200?|
|PCIe Gen Support||PCIe 3.0 (48 Lanes)||PCIe 3.0 (48 Lanes)||PCIe 3.0 (48 Lanes)||PCIe 4.0 (64 Lanes)||PCIe 5.0 (80 lanes)||PCIe 5.0 (80 Lanes)||PCIe 6.0 (128 Lanes)?||PCIe 6.0 (128 Lanes)?|
|TDP Range (PL1)||140W-205W||165W-205W||150W-250W||105-270W||Up To 350W||Up To 375W?||Up To 400W?||Up To 425W?|
|3D Xpoint Optane DIMM||N/A||Apache Pass||Barlow Pass||Barlow Pass||Crow Pass||Crow Pass?||Donahue Pass?||Donahue Pass?|
|Competition||AMD EPYC Naples 14nm||AMD EPYC Rome 7nm||AMD EPYC Rome 7nm||AMD EPYC Milan 7nm+||AMD EPYC Genoa ~5nm||AMD EPYC Bergamo||AMD EPYC Turin||AMD EPYC Venice|