Intel Teams Up With Navy To Develop Advanced Multi-chip Package Prototypes
Chipmaker Intel Corporation (NASDAQ:INTC) announced on Friday that its subsidiary Intel Federal LLC has won a government contract that will help the United States to shift its defense industrial manufacturing base to the homeland. Intel is one of the three companies in the world that is capable of manufacturing processors on advanced processing nodes, and the contract is part of the broader American shift to ensure access to critical semiconductors and other supplies in the face of rising tensions with China.
Intel Will Focus On Developing Prototypes That Will Integrate Government Chips With Its Products
The contract award will be monitored by the U.S. Navy's Naval Surface Warfare Center - Crane Division (NSWC Crane) in Crane, Indiana. It covers the second phase of the State-of-the-Art Heterogeneous Integration Prototype (SHIP) program that will secure government access to Intel's packaging facilities in Arizona and Oregon.
In its statement, the company did not specify a material value of the contract. As the contract title suggests, the cooperation will cover Intel developing prototypes that 'lump' together multiple chips in a single package - in a technology referred to in the semiconductor industry as 'chiplets'.
Chiplets are the industry's response to the increasing problems that chip fabricators face as node-scaling increases the cost of manufacturing dies. A silicon die is costlier to manufacture as process nodes advance, and chiplets allow companies to reduce costs by manufacturing smaller dies and then linking them together by using Through-Silicon-Vias (TSVs), short wires and interposers amongst other technologies.
Intel introduced its Foveros 3D die-stacking technology in 2018 at its Architecture Day. The design involves placing two different types of chips, such as a central processing unit and a memory chip, on an interconnect which is then connected to the packaging material that connects to the motherboard.
A key advantage offered by Intel's technology is that the interposer within the packaged components is not passive. What this means is that the material itself actively monitors variables such as current leakage and performance and therefore enables a controlled environment. In addition to Foveros, the company also connects multiple chips through its Embedded Multi-Die Interconnect Bridge (EMIB) technology that removes TSVs from the connecting equation and Co-EMIB, which is a process that combines EMIB and Foveros.
EMIB features metal connections within a silicon bridge on which two separate dies are placed and owing to the high density of the microbumps that connect to the silicon bridge, the power efficiency of the entire package is also improved. The Navy intends to use all three of these technologies to integrate its purpose-built chips with Intel's products such as CPUs, Field-Programmable Gate Arrays (FPGAs) and application-specific integrated circuits (ASICs).
The announcement came as Intel celebrated its 2020 manufacturing day, on which the chipmaker showcases its prowess in semiconductor fabrication. At the event, the company revealed that it produces ten billion transistors each second and that it has packed four hundred million of the circuits into one mm² of a chip manufactured using its 10-nm manufacturing process.
However, earlier this year the chipmaker also admitted to problems with its next-generation chip manufacturing process referred to as 7nm. In its earnings call for the second quarter of 2020, Intel revealed that its 7nm products would be delayed by six months to 2023 as it suffers from yield problems for the process. Chiplet technologies are one method that lets companies avoid such problems as they allow them to produce smaller chip dies and then integrate them into a single package. Yield is inversely proportional to die size and the term refers to the usable amount of transistors that remain once a chip has been fabricated or 'printed'.
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