Recent Intel Patches within Linux have confirmed that 14th Gen Meteor Lake CPUs will be making use of L4 cache that should assist the Arc Xe-LPG GPUs.
Intel Meteor Lake CPUs Adopt of L4 Cache To Deliver More Bandwidth To Arc Xe-LPG GPUs
The confirmation was published in an Intel graphics kernel driver patch this Tuesday, reports Phoronix. The patch states that Intel's Meteor Lake GT (Graphics Tile) won't be able to allocate LLC(Last Level Cache) and only the CPU can. There's also support for ADM/L4 cache mentioned which is a brand-new L4 cache coming to Meteor Lake.
Coelacanth-Dream sheds more light on this and states that on the previous "conventional" Intel CPUs, we have seen the CPU cores and the GPU cores share the LLC. It was also possible for this cache to be allocated to the GPU but with Meteor Lake CPUs that changes and the GPU cannot use the LLC anymore. The LLC has not been removed but instead, it would only be used by the CPU.
So that raises the question as to what the Intel Meteor Lake GPU is going to use. Intel's Meteor Lake CPUs will be featuring a big upgrade to their graphics engine which shares the same design and DNA as the Alchemist architecture that we got on Arc discrete graphics series. Now a Xe-LPG (Low-Power) version of the same chips is heading to Meteor Lake CPUs in the form of a tGPU (Tile GPUs) which will have their own separate slab on the Meteor Lake chip and deliver some amazing performance numbers over the past UHD and Iris Xe solutions.
These Arc Xe-LPG integrated GPUs will use what is said to be an L4 cache labeled as "ADM". There is currently no size mentioned for the L4 cache but it is likely that this is going to be an eDRAM cache similar to the ones featured on older Broadwell CPUs. This sounds a lot like the Crystal Well eDRAM that offered up to 128 MB of cache to the higher-end Iris Pro integrated GPUs all the way back in 2013.
We have seen that GPU makers have been increasing the on-die and off-die cache for their GPUs. AMD uses its Infinity Cache as a proper LLC for its RDNA GPUs. The most recent implementation on the RDNA 3 GPUs pushed the Infinity Cache off the GPU die and to its separate MCD. NVIDIA has also upgraded the amount of L2 cache on its GPUs with up to 16x increases on the flagship Ada GPUs. Meanwhile, L4 cache, while not as effective as L1/L2 (due to large misses) can still achieve a boost in performance through higher bandwidth and capacities for integrated GPUs which are generally bandwidth starved.
But unlike Crystal Well which was a memory-side L4 cache that could be allocated to virtually any part of the chip, the ADM/L4 is specifically allocated to the Intel Meteor Lake's GPU portion. Based on the die layout presented by Intel during HotChips 34, it looks like the L4 cache might fit into the SOC Tile but that remains to be seen. For now, having an extra L4 cache dedicated to the iGPU can have some positive effects but nothing is for certain until we see the chips in action.
Intel Mobility CPU Lineup:
| CPU Family | Panther Lake | Lunar Lake | Arrow Lake | Meteor Lake | Raptor Lake | Alder Lake |
|---|---|---|---|---|---|---|
| Process Node (CPU Tile) | Intel 18A | TSMC N3B | TSMC N3B | Intel 4 | Intel 7 | Intel 7 |
| Process Node (GPU Tile) | TSMC N3E / Intel 3 | TSMC N3B | TSMC 5nm | TSMC 5nm | Intel 7 | Intel 7 |
| CPU Architecture | Hybrid | Hybrid (Dual-Core) | Hybrid (Triple-Core) | Hybrid (Triple-Core) | Hybrid (Dual-Core) | Hybrid (Dual-Core) |
| P-Core Architecture | Cougar Cove | Lion Cove | Lion Cove | Redwood Cove | Raptor Cove | Golden Cove |
| E-Core Architecture | Darkmont | N/A | Skymont | Crestmont | Gracemont | Gracemont |
| LP E-Core Architecture (SOC) | Darkmont | Skymont | Crestmont | Crestmont | N/A | N/A |
| Top Configuration (Compute Tile) | 4+8 (H-Series) | 4+4 (MX Series) | 6+8 (H-Series) 2+8 (U-Series) | 6+8 (H-Series) 2+8 (U-Series) | 6+8 (H-Series) 8+16 (HX-Series) | 6+8 (H-Series) 8+8 (HX-Series) |
| Max Cores / Threads | 16/16 | 8/8 | 14/14 | 14/20 | 14/20 | 14/20 |
| AI NPU | NPU5 (50 TOPS) | NPU4 (48 TOPS) | NPU3.5 (13 TOPS) | NPU3 (11 TOPS) | NPU2 (7 TOPS) | NPU2 (7 TOPS) |
| Planned Lineup | Core Ultra 300 | Core Ultra 200V | Core Ultra 200 | Core Ultra 100 | 14th/13th Gen | 12th Gen |
| GPU Architecture | Xe3-LPG (Battlemage) | Xe2-LPG (Battlemage) | Xe-LPG+ (Alchemist) | Xe-LPG (Alchemist) | Iris Xe (Gen 12) | Iris Xe (Gen 12) |
| Xe Cores (Max) | 12 Xe3 Cores | 8 Xe2 Cores | 8 Xe Cores | 8 Xe Cores | 96 EUs (768 Cores) | 96 EUs (768 Cores) |
| Memory Support | LPDDR5X-9600 | LPDDR5X-8533 | DDR5-5600 LPDDR5-7500 LPDDR5X-8533 | DDR5-5600 LPDDR5-7400 LPDDR5X - 7400+ | DDR5-5200 LPDDR5-5200 LPDDR5-6400 | DDR5-4800 LPDDR5-5200 LPDDR5X-4267 |
| Memory Capacity (Max) | 128 GB | 32 GB | 128 GB | 96 GB | 64 GB | 64 GB |
| Thunderbolt Support | TB5 | TB5 | TB5 | TB4 | TB4 | TB4 |
| WiFi Capability | WiFi 7 | WiFi 7 | WiFi 7 | WiFi 6E | WiFi 6E | WiFi 6E |
| TDP | 17-45W | 17-30W | TBD | 7W-45W | 15-55W | 15-55W |
| Launch | 2H 2025 | 2H 2024 | 2H 2024 | 2H 2023 | 1H 2023 | 1H 2022 |
About the author: A Software Engineer by training and a PC enthusiast by passion, Hassan Mujtaba serves as Wccftech's Senior Editor for hardware section. With years of experience in the industry, he specializes in deep-dive technical analysis of next-generation CPU and GPU architectures, motherboards, and cooling solutions. His work involves not only breaking news on upcoming technologies but also extensive hands-on reviews and benchmarking.
Follow Wccftech on Google to get more of our news coverage in your feeds.
