Yesterday, we reported a few key details of Intel's next-gen CPUs which feature a very LEGO-Esque design thanks to the 3D Foveros packaging technology. The new CPUs that will be putting the tech to good use include Meteor Lake, Arrow Lake, and Lunar Lake. Today, at Hot Chips 34, Intel is giving us a more detailed look at what goes into developing the Meteor Lake CPUs and beyond.
Intel 3D Foveros Packaging Tech Brings LEGO-Like Design To Next-Gen Meteor Lake, Arrow Lake & Lunar Lake CPUs
The key enabler of Intel's next-gen CPUs is Foveros, an advanced inter-die chiplet packaging tech. Foveros will come in three flavors, starting first with the standard design that will be used for high-yield and high-volume production, moving on to Foveros Omni that mixes and matches tiles in the base die complex, offering up to 4x interconnect bump density vs EMIB and lastly, Foveros Direct which offers 16x interconnect density versus the original Foveros while delivering lower latency, higher bandwidth and reduced power/die requirements. Following are the base specs for the trio of Foveros solutions:
- Foveros: 50-25um (Bump Pitch), >400-1600/mm2 (Bump Density), 0.156 pJ/bit (Power)
- Foveros Omni: 25um (Bump Pitch), 1600/mm2 (Bump Density), <0.15 pJ/bit (Power)
- Foveros Direct: <10 Microns (Bump Pitch), >10,000/mm2 (Bump Density), <0.05 pJ/bit (Power)
Beyond Alder Lake and Raptor Lake CPUs which are the first designs to feature a hybrid core layout, Intel is planning to utilize its 3D Foveros packaging to usher in its own multi-chiplet era. Chipzilla has planned on releasing three products that will leverage this technology. The next-generation processors include the 14th Gen Meteor Lake, 15th Gen Arrow Lake, and 16th Gen Lunar Lake families. Some of the main highlights of these CPUs would be:
- Intel Next Generation 3D Client Platform
- Disaggregated 3D Client architecture with CPU, GPU, SOC, and IO Tiles
- Base tiles for Meteor Lake and Arrow Lake to interconnect tiles with Foveros
- Open "Chiplet" ecosystem through universal chiplet interconnect express (UCIe)
Starting first with Intel Meteor Lake, the company showed off a brand new chip layout which gives us a better look at the various tiles or chiplets (as you like to refer to them) with various IPs. The quad-tile layout includes the CPU Tile, Graphics Tile, SOC Tile, and IOE Tile.
Intel did disclose the specific nodes these tiles would be based upon. The main CPU tile will be using the "Intel 4" or 7nm EUV process node while the SOC Tile and IOE Tiles will be fabricated on TSMC's 6nm process node (N6). Intel calls Meteor Lake the first step into the chiplet ecosystem in the client segment. According to industry sources, this isn't the case and the tGPU for the Meteor Lake CPUs has always been a TSMC 5nm (N5) design.
So starting with the dissection of each tile, first up, we have the Compute Tile which is fully scalable across various core counts, core generations, nodes, and cache. Intel can mix and match not just different core architectures within its Foveros 3D package CPUs such as Meteor Lake but they can also scale up or down to a different node.
The same is true for the graphics tile which can be scaled in terms of core count, node and cache too. These diagrams are just for illustration purposes but they show a tGPU block scaling from 4 Xe cores (64 EUs) up to 12 Xe Cores (192 EUs). However, based on the die shot in the same picture, we can see 8 Xe Cores (128 EUs).
The SOC Tile can also be scaled up or down depending on the SKU. The main blocks here are the Low-Power IP (referring to the VPU), SRAM, IO, and a scalable voltage design. The same is true for the last Tile, the I/O Extender, or IOE in short. The tile is fully scalable in terms of the number of lanes, bandwidth, protocols, and speed.
With the tiles out of the way, it's time to put together everything and for that, Intel has shown a breakdown of how the CPU dies are arranged together. The top layer has a back-side metallization and is also where the Foveros passive die sits. Right below these is the known good tiles that we've just discussed above. These tiles are connected to the Base Tile using a 36um pitch (die-to-die) inter-connect. The Base Tile comes with large capacitance and has metal layers for IO/power delivery and D2D routing.
Intel also provides a close-up of the Base Tile's metal layer which features 3D capacitors and die-to-die power delivery plus package I/O routing. Each metal layer is modular with active silicon for logic and memory. The top and bottom have package bumps for interconnecting with the top & bottom layers.
The configuration shown here is also a mobile-specific chip with a 6+8 (6 P-Cores + 8 E-Cores) layout. You can also note that there are two D2D (Die-To-Die) links between the CPU/IOE Tile and the Graphics Tile leading into the SOC Tile. This is part of the Foveros 3D Packaging and the blue team states that there's a passive interposer on top of the main chiplets which is based on a 22nm (FFL) process from Intel itself. This interposer currently serves no purpose but the company plans to use active chiplets within it in the future with more advanced packaging technologies. The Intel Meteor Lake CPUs don't utilize EMIB technology.
The FDI (Foveros Die Interconnect) technology offers:
- A Low Voltage CMOS Interface
- High Bandwidth, Low Latency
- Synchronous & Asynchronous Signaling
- Low Area Overhead
- Operation @ 2GHz, 0.15-0.3 pJ/bit
The Interconnects between the CPU and the SOC have a mainband width of around 2K (2x IDI), the Graphics and SOC tiles have a interconnect mainband width of around 2K too (2x iCXL) while the SOC and IOE tiles have a mainband width around 1K (IOSF, 4x Display Port).
Another key area where Intel's Meteor Lake CPUs have improved a lot is the maximum turbo power capability. Since its inception and with the help of co-optimizations, the Meteor Lake chips can achieve higher turbo power capabilities than the previous generation Alder Lake CPUs while utilizing the brand new "Intel 4" process node. The total capacitance has also touched 500 for the Meteor Lake Base Tile.
Intel gives us an old-school comparison between a Haswell and Meteor Lake CPU as far as their I/O capabilities are concerned.
Another aspect that was touched upon by Intel is pricing. With costs of next-gen wafer prices going up with every new node, the cost of developing a monolithic die is also going to go up.
If you were to take Meteor Lake as it is and design it monolithically on a leading process node, I would say it actually is extremely competitive with that if not actually cheaper.
Intel shows that a disaggregated design like Meteor Lake with Tiled-architecture can deliver higher performance, higher transistor performance uplifts, & better IP refresh pace across various process nodes, all at higher power efficiency versus a monolithic solution.
Intel revealed that its Meteor Lake CPUs will scale from <10W to over 100W SKUs, offering CPU performance of a monolithic design in a disaggregated package. Furthermore, Intel clarified that 14th Gen Meteor Lake & 15th Gen Arrow Lake CPUs are indeed heading to both Desktop and Mobile platforms.
The Intel Meteor Lake CPUs are aiming for the 2023 release window while Arrow Lake will start shipping in 2024 as originally planned. Details on the next-generation LGA 1851 socketed platform for Meteor Lake & Arrow Lake CPUs can be found here.
Intel Meteor Lake-P (6+8) CPU Chip Layout:
As far as 16th Gen Lunar Lake CPUs are concerned, the family is said to be originally aimed at the 15W low-power mobile CPU segment however those original plans can always change since the product is still a few years away from launch.
Furthermore, it won't be the first time Intel sticks with a mobile-only or partial-desktop release for a CPU family. We have already seen them do this with Broadwell and more recently with the Ice Lake and Tiger Lake CPU families.
Intel Mobility CPU Lineup:
|CPU Family||Arrow Lake||Meteor Lake||Raptor Lake||Alder Lake|
|Process Node (CPU Tile)||Intel 20A '5nm EUV"||Intel 4 '7nm EUV'||Intel 7 '10nm ESF'||Intel 7 '10nm ESF'|
|CPU Architecture||Hybrid (Four-Core)||Hybrid (Triple-Core)||Hybrid (Dual-Core)||Hybrid (Dual-Core)|
|P-Core Architecture||Lion Cove||Redwood Cove||Raptor Cove||Golden Cove|
|Top Configuration||TBD||6+8 (H-Series)||6+8 (H-Series)||6+8 (H-Series)|
|Max Cores / Threads||TBD||14/20||14/20||14/20|
|Planned Lineup||H/P/U Series||H/P/U Series||H/P/U Series||H/P/U Series|
|GPU Architecture||Xe2 Battlemage 'Xe-LPG'|
Xe3 Celestial "Xe-LPG"
|Xe-LPG 'Xe-MTL'||Iris Xe (Gen 12)||Iris Xe (Gen 12)|
|GPU Execution Units||192 EUs (1024 Cores)?||128 EUs (1024 Cores)|
192 EUs (1536 Cores)
|96 EUs (768 Cores)||96 EUs (768 Cores)|
LPDDR5X - 7400+
|Memory Capacity (Max)||TBD||96 GB||64 GB||64 GB|
|Thunderbolt 4 Ports||TBD||4||4||4|
|WiFi Capability||TBD||WiFi 6E||WiFi 6E||WiFi 6E|
|Launch||2H 2024?||2H 2023||1H 2023||1H 2022|