Intel bLLC Reportedly Will Be Only Present On Unlocked Nova Lake CPUs, 144 MB of Boosted Cache To Tackle AMD’s 3D V-Cache Chips

How We Rate Rumors

• 0-20%: Unlikely - Lacks credible sources
• 21-40%: Questionable - Some concerns remain
• 41-60%: Plausible - Reasonable evidence
• 61-80%: Probable - Strong evidence
• 81-100%: Highly Likely - Multiple reliable sources

RUMOR ASSESSMENT

70%

Probable

Source 5/5

Corroboration 2/5

Technical 4/5

Timeline 3/5

Some of the upcoming Nova Lake SKUs are already rumored to feature higher L3 cache, but it appears that Intel is targeting only unlocked variants.

Intel to Equip Only Unlocked Nova Lake CPUs with bLLC, Delivering Higher Cache Than the Rest

Not long ago, we heard that Intel might be preparing dedicated competitors to AMD's X3D chips, and these CPUs will be first released in the Nova Lake lineup. Intel Nova Lake will be available for both desktop and mobile platforms, and as per some previous reports, only mid-range SKUs will have the additional cache known as bLLC or Big Last Level Cache.

Today, one of the prominent leakers, @Jaykihn, reported that only "Unlocked" Nova Lake SKUs will have the bLLC. Now the number of SKUs with bLLC further boils down to a few, but keep in mind that we don't have concrete evidence to suggest that higher-end SKUs with overclocking enabled won't have bLLC. It could go any way, but most reports suggest that SKUs with 8+16 Core configuration will be the ones to have the additional cache.

That said, the Core Ultra 7 and 9 series will have a higher core count configuration, and we only have the Core Ultra 5 series to boast an 8 P-core + 16 E-core config with an additional 4 LP-E cores. These are the only SKUs rumored to get the 144 MB of total LLC, but some rumors also suggested that the Core Ultra 9 may also boast up to 180 MB of total LLC with dual bLLC tiles.

As for the 144 MB figure, that's in addition to the L2 and L3 caches onboard the compute tile for each respective P-Core and E-Core architectures. The bLLC cache was expected to be similar to how Intel arranges that on its Clearwater Forest chips; however, the source states that it resides on the compute tile too.

Nova Lake Lineup Configuration according to previous reports:

• Core Ultra 9 - 16 P-Cores + 32 E-Cores + 4 LP-E Cores (150W)
• Core Ultra 7 - 14 P-Cores + 24 E-Cores + 4 LP-E Cores (150W)
• Core Ultra 5 - 8 P-Cores + 16 E-Cores + 4 LP-E Cores (125W) + bLLC Variant
• Core Ultra 5 - 8 P-Cores + 12 E-Cores + 4 LP-E Cores (125W) + bLLC Variant
• Core Ultra 5 - 6 P-Cores + 8 E-Cores + 4 LP-E Cores (125W)
• Core Ultra 3 - 4 P-Cores + 8 E-Cores + 4 LP-E Cores (65W)
• Core Ultra 3 - 4 P-Cores + 4 E-Cores + 4 LP-E Cores (65W)

Do take this information with a grain of salt, but it appears that Intel wants to maximize the performance potential by equipping bLLC only on unlocked SKUs. This makes sense since AMD has already cracked the code to allow full overclocking on Ryzen 9000X3D chips. Whether Intel will deploy bLLC on locked chips or not will entirely depend on the success of unlocked CPUs with bLLC, but we are eager to see how close Intel gets to AMD in the performance department.

AMD itself will try to go the next level with future Zen 6 "Ryzen" CPUs featuring 3D V-Cache, so game on in the CPU segment with big last-level caches.

Nova Lake-S vs Arrow Lake-S

Family	Nova Lake-S	Arrow Lake-S
Core Count (Max)	52	24
Thread Count (Max)	52	24
Max P-Cores	16	8
Max E-Cores	32	16
Max LP-E Cores	4	0
Max Cache (L2+L3)	160-320 MB	76 MB
Max bLLC Cache	144-288 MB	N/A
DDR5 (1DPC 1R)	8000 MT/s	7200-6400 MT/s
PCIe 5.0 Lanes (Max)	36	24
PCIe 4.0 Lanes (Max)	16	4
Socket Support	LGA 1954	LGA 1851
Max TDP (PL1)	125-175W	125W
Max Power	~700W (Dual) ~350W (Single)	~400W
Launch	2H 2026	1H 2026

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