Exclusive: Here Is Intel’s First 7nm GPU Xe HPC Diagram With Correct Annotations

Submit

Intel recently unveiled one of the biggest chips we have ever seen and we instantly reached out to some of our sources for further details. While we had an idea of what to expect due to technical disclosures on Architecture Day we were still blown away by what we learned. You are looking at what is the first Intel 7nm die shot (of a packaged product) and courtesy of our sources, the full correct annotation for what you are seeing is finally here.

Intel's Xe HPC 2-tile (PVC) GPU uses a blend of Intel 7nm, Intel 10nm ESF, and TSMC 7nm process technology brought together by Foveros

Everything mentioned in this article has been confirmed and cross-referenced by at least two of our sources and represents the correct annotations for the Xe HPC die shot. The Intel Xe HPC 2-tile package (which is pretty much the Ponte Vecchio GPU in its early stages) shown off by Intel Chief Architect Raja Koduri is an absolute marvel in terms of the technology used.

The die shot is nothing less than a technical showcase with some of Intel's most advanced process and packaging technologies - and no that is not an exaggeration. It shows not only the first-ever 7nm die shot (in a packaged product) of Intel's in-house 7nm process but also shows EMIB in use with Foveros 3D Packaging. You can also spot the promised mix and match philosophy with parts from TSMC and new features like Rambo Cache as well.

Let's start from the top. The Xe Link/IO Tile can be seen in the top right and bottom right corners of the package and has been fabricated on TSMC's 7nm process. Interestingly, the die shot also contains two different sized HBM2 tiles which can be seen on either side of the main tiles. And yes, that is HBM2 and not simply HBM. The star attraction of both tiles is the compute die (16 in total) and was fabricated on Intel's own 7nm process. While a lot of people assumed that the vertical dies surrounding the compute die are either XEMF Scalable Memory Fabric or Rambo Cache - that is not actually true. The vertical dies on the right, left, top and bottom positions are actually passive die stiffeners that contain no logic on board.

The Rambo Cache is actually in the middle and is fabricated on Intel's 10nm Enhanced Super Fin process. The 10nm base die is actually underneath the tiles you can see in the picture and the same goes for EMIB, which is under the passive dies and HBM2. Since this package utilizes Intel's 3D Foveros packaging, there is a lot happening which is out of sight and until we get a detailed 3D diagram with layers, it would be a bit hard to visualize just how complex this particular package is.

Raja teased that there are 7 advanced technologies at play here, and by our calculation, these would be:

  • Intel 7nm
  • TSMC 7nm
  • Foveros 3D Packaging
  • EMIB
  • Enhanced Super Fin
  • Rambo Cache
  • HBM2

Keep in mind, however, that the package you are seeing is simply the first iteration (read: prototype) of Intel's upcoming Ponte Vecchio chip. Considering it is due sometime in late 2021 or early 2022, the first power on is very very good news for Intel enthusiasts and shows that the company is coming along nicely as far as the roadmap goes. Ponte Vecchio will be utilized in the Aurora supercomputer and there were a lot of concerns on whether Intel would be able to meet the deadline. The answer to that, it seems, is yes.

Submit