Intel’s 18A-P Debuts Power Boost, an Industry-First Dual-Contact Transistor That Squeezes More Frequency From the Same Chip Footprint

Intel is sharing more details of its 18A-P process technology, which is expected to see some major customer momentum.

Intel's 18A-P Process Tech Is Just As Key To Its Foundry Business As 14A, And Chipzilla Is Further Sharing Its Benefits Over 18A

Semiconductor manufacturing is a super-hard business, and Intel is working really hard to get its Foundry up to standards through the accelerated development of advanced process nodes and packaging technologies. Given its immense progress with 18A and the buzz surrounding its next process technologies, such as 14A, Intel Foundry is shaping up well. But they have a lot to prove to their customers, still.

As such, Intel is not rushing things. Sure, customers would like to see the latest & greatest being rolled out as soon as possible, but Intel is offering something unique to its customers, a node that is specifically designed for them and builds upon the foundation of one of its successful 18A offerings, called 18A-P.

Intel's 18A-P was already teased a while back, and today at VLSI 2026, Intel is giving the full run-down of this key process node. Intel confirms that 18A-P is now in risk production, & comes with various new features such as Power Boost.

So starting with the details, first we have the performance and power uplifts. Intel's 18A-P delivers a 9% boost in performance at the same power, or 18% lower power at the same performance (on a standard ARM core sub-block) versus 18A. It builds upon the same GAA and backside power foundation and offers full design-rule compatibility with Intel 18A, allowing reuse of existing IP and design flows.

Intel pitches 18A-P's low-voltage gains as great for energy-efficient AI, HPC, & emerging compute applications. Besides that, 18A-P also introduced material innovations that offer a 20-40% improvement in thermal resistance when using enhanced EDA workflows. There's also a 10-30% improvement in through-silicon vias resistance.

The full list of features for 18A-P is listed below:

• Intel 18A-P delivers 9% higher performance at iso‑power or 18% lower power at iso-performance compared to Intel 18A, alongside enhanced thermal characteristics and expanded design flexibility.
• Unveiled Power Boost, Intel 18A-P’s new dual contact, low resistance transistor option enabling increased drive current and greater frequency at matched capacitance.
• 20-40% improved thermal resistance through both materials and design innovations.
• 10-30% improved via resistance (referring to the vertical connections between the layers of a chip) using geometric and materials optimizations.
• Mobility enhancement through PMOS via strain engineering, letting current move through the transistor more efficiently.
• New low-power and high-performance transistor options.
• New fifth logic Vt pair between ULVT and LVT (an additional fifth Vt option for designers to balance speed and power).
• Intel 18A‑P is fully design rule compatible with Intel 18A, enabling straightforward reuse of existing IP and design flows.
• Similar to Intel 18A, Intel 18A-P offers two cell heights (180nm and 160nm), a contacted poly pitch of 50nm.

Now, coming to the new Power Boost feature, which Intel calls the industry's first implementation of a novel dual-contact architecture that is enabled by PowerVia backside power delivery for both NMOS and PMOS transistors. With this, 18A-P offers enhanced performance at matched footprint for power-constrained applications. 18A-P offers 160nm and 180nm high transistor cells.

Another key area of focus is improvements to the backside power delivery. With backside power, Intel is able to shift major power routing to the rear of the wafer, reducing congestion by reducing stress on the frontside interconnect. With backside power, Intel can achieve a 11% area reduction along with shorter wires and fewer vias. Intel 18A-P continues to leverage backside power with 32 nm metal processes, which make for a cost-effective design and reduce the manufacturing steps when building next-generation chips.

Besides 18A-P, Intel also talked about other breakthrough research by its Foundry division, which includes:

• Efficient power management logic using 300 mm GaN and silicon technology: Following up on Intel Foundry's recent achievement of creating the world's thinnest GaN chiplet, our engineers presented another breakthrough innovation at VLSI 2026. Together with collaborators from the University of California, San Diego, the team proved it’s practical to build efficient multi-thousand-gate digital control circuits directly on one chip by using a hybrid GaN nMOS and silicon pMOS approach in a 300 mm manufacturing process. The team achieved a record power-delay product (PDP) of just 6.2 attojoules (aJ) per stage — over 1,000x more efficient than prior GaN logic approaches, and showcased the largest-scale integrated logic on GaN to date.⁴ This future technology will enable on-chip control integration by reducing cost, size, and complexity while improving system performance.
• CFET integration at 45 nm gate pitch on a 2x2 ribbon stack: CFET 3D transistors combine NMOS and PMOS transistors stacked vertically for more performance in a smaller space. Our team built working logic circuits at a very small size (45 nm pitch), along with advanced integration features including backside power delivery, direct backside contacts, and novel epi‑epi vias as a compact vertical connection. We demonstrated a bonding technique for performance improvement without introducing parasitic penalties. In addition, we showed how device depopulation enables a common gate architecture by selectively removing unused devices within a CFET stack to reduce process complexity and improve design flexibility.
• Performance improvement from subtractive Ru interconnects with airgap: Our team demonstrated a next‑generation interconnects approach featuring subtractive Ru wiring with airgap, marking the first integration of this metallization scheme with functional RibbonFET devices on a test chip. At matched leakage, it achieves roughly a 2% improvement in circuit performance as compared to conventional copper interconnects, driven by a capacitance reduction of up to 35% from the airgap. The research also shows up to 50% reduction in lower and upper via resistance, thereby improving vertical connections.⁵ Together, these results deliver faster and more efficient signal transmission and provide a scalable path for improving the performance of interconnects at tight pitches.

At Computex 2026, Intel officially announced Diamond Rapids, its next-generation Xeon CPUs, to be built on the 18A-P process technology. This is another sign of confidence that Intel presents to its customers that its process technologies aren't great for external chips, but also great for their own chips under development.

Intel Foundry has already found some major customers, as per recent reports. TeraFab, SpaceX, and Apple are just a few of these names that have made it to the web. NVIDIA, Google, & others are also expected to utilize the Foundry in some way for their own chips as the supply-demand gap due to the AI crunch continues to expand.

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