Intel: Achieved 10nm HVM with Ice Lake Mobility SOC – 2x AI Performance, Gen 11 Graphics and Thunderbolt 3

Jan 7

Intel has unveiled its Ice Lake mobility SOC which has achieved high volume manufacturing (or HVM) on the 10nm process – which is great news for enthusiasts because it means you will finally be able to get their hands on an Intel 10nm powered product – en masse. The Ice Lake SOC is based on the Sunny Cove architecture which already offers significant improvements over Skylake.

Intel’s 10nm Ice Lake mobility SOC will be powering 2 in 1s and notebooks – has already achieved HVM, on the shelves by holiday 2019

Intel’s 10nm Ice Lake SOCs will pack Intel Gen 11 graphics capable of driving 4K screens and have very impressive battery life. Apart from that the new and improved sunn cove architecture will allow the processors to achieve roughly 2x the AI performance as compared to Skylake in specific inference workloads. It also includes Thunderbolt 3 and high-speed wifi included on board.

The fact that Intel has achieved HVM with *any* 10nm product, of course, is the actual highlight of the announcement – because this is something they have not been able to achieve thus far. Intel has also given a timeline for the product to hit the shelves – which is holidays 2019 (ie late 2019).

Ice Lake is based on Sunny Cove, which is a significant improvement over Skylake processors and all of it has to do with design innovation. The Sunny Cove next-generation processors will be deeper, wider and smarter – as per the details revealed during the Intel architecture day event.

Sunny Cove processors have received a 50% increase in the size of the L1 data cache as well as a larger L2 cache. They also feature larger operations cache and a larger 2nd level translation lookaside buffer. The result is a processor that has received a significant increase in key structures can execute code with much more depth than Skylake.

Sunny Cove processors are also wider than Skylake. They have 5-wide allocations instead of 4 and 10 execution ports instead of 8. They have also received two times the L1 store bandwidth thanks to 4 AGU instead of 3 and 2 data stores. Not only that, but greater execution capability is now part of the architecture. SIMD, Shuffle and LEA units have been added to the Vector and Integer blocks.

New algorithms that can handle scale better and increase branch prediction accuracy (this reminds me, hardware mitigations for Spectre v1 are already shipping and Sunny Cove will include hardware mitigations for Spectre v2). The effective load latency has also been reduced.