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An Intel director believes that future transistor designs could make the need for advanced lithographic equipment less compelling when manufacturing high-end semiconductors. ASML's extreme ultraviolet (EUV) lithography machines are the backbone of modern-day advanced chip manufacturing as they enable firms like TSMC to print extremely small circuits on a silicon wafer. However, the Intel director believes that future transistor designs, which include gate-all-around FET (GAAFET) and complementary FET (CFET), will rely more on post-lithography steps in fabrication and reduce the overall importance of lithography in manufacturing high-end chips.
Etching Companies Can Play Greater Role In Future Semiconductor Fabrication, Says Intel Director
In a discussion posted on the investment research platform Tegus and shared on X, an unnamed Intel director shares that future transport designs will rely less on advanced lithographic equipment and more on etching technology. While lithography machines, such as ASML's advanced EUV and high-NA EUV scanners are the most widely discussed chip making equipment particularly due to export-control restrictions, manufacturing a chip involves other steps as well.
Lithography is the first step in the process, and it transfers designs to the wafer. These designs are then cemented through processes such as deposition and etching. Deposition sees chip manufacturers deposit materials on the wafer while etching selectively removes them to create patterns of transistors and circuits for chips.
As per the Intel director, new transistor designs such as GAAFET and CFET can reduce the importance of lithography machines in the chip manufacturing process. These machines, particularly EUV scanners, have played a crucial role in making chips with 7-nanometer and advanced technologies due to their ability to transfer or print small circuit designs on the wafer.
Once the designs are transferred, etching removes the excess material from the wafer to finalize them. Most current transistor designs follow the FinFET model where the transistors are connected to the insulating material at the bottom and pass through a gate that controls electrical flow within them. Newer designs, such as GAAFET envelop the gate around the transistors, with transistor groups located parallel. Ultra high-end transistor designs, such as CFET, stack the transistor groups on top of each other and save space on the wafer.
As per the Intel director, since GaaFET and CFET designs "wrap" the gate from all sides, removing excess material from the wafer is crucial. The 'wrapping' requires chip manufacturers to remove excess material laterally, so instead of increasing the time a wafer spends in the lithography machine to reduce feature sizes, manufacturers will focus more on removing the material through etching.
The increasing importance of the 'lateral' direction in chip fabrication means that high NA EUV machines are "less likely" to be as critical to chip manufacturing as their predecessors, EUV scanners, were to manufacture chips on 7-nanometer or advanced technologies. The end result of the shift is that it "reduces reliance on the minimum feature because you can still get high density, not just on a given plane, but vertically, also," believes the executive.
Director at Intel explains why ASML has been struggling due to GAA, and will struggle with the move to CFETs as well (via Tegus). The bright spot in terms of order flow can be high-NA adoption later this decade, or EUV multiple patterning, but clearly order flow will be highly… pic.twitter.com/ZoRvJJHC2n
— Tech Fund (@techfund1) June 16, 2025
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