Alleged AMD Zen 5 Benchmarked In Dual EPYC ES CPU Configuration: 64 Cores Per Chip Up To 3.85 GHz, Faster Than 96-Core Genoa

The first and alleged performance benchmark of an AMD Zen 5 system running dual next-gen EPYC Turin CPUs has leaked out by Moore's Law is Dead.

AMD's Dual EPYC Turin ES CPUs With Zen 5 Core Architecture Allegedly Benchmarked, Faster Than 96-Core Genoa Chips

According to Moore's Law is Dead, the rumor outlet has received what seems to be the first AMD Zen 5 CPU benchmarks. The benchmarks are not of a consumer-level Ryzen chip but of an EPYC dual-system configuration. The rumored chip could be part of the AMD EPYC Turin family which is expected to launch next year.

So before talking about benchmarks, we have to talk about the specs that this alleged chip boasts. First of all the CPU is a very early engineering sample so a lot can change between now and during the time of its launch. The AMD EPYC Turin ES CPU with Zen 5 core architecture features 64 cores and 128 threads and since this is a dual-socket configuration, it shows up as 128 cores and 256 threads. Each chip carries the same amount of L2 and L3 cache as the Zen 4 cores but the L1 cache sees a small upgrade.

The L1 cache goes from 64 KB on Zen 4 to 80 KB on Zen 4, marking a 25% increase. The L2 cache is 64 MB per chip (1 MB per core) and the L3 cache is 256 MB (4 MB per core). The CPU clocks seem to be rated at 2.3 GHz base & 3.85 GHz boost which might seem very high for an engineering sample of a CPU that releases more than a year from now. That's already 4% higher than the boost clocks of the AMD EPYC 9654 Genoa chip but during a recent projection slide, ex-AMD architect Jim Keller pointed out that Zen 5 might either hit or exceed the 4 GHz clock barrier on servers.

Now coming to the main action which is the performance benchmark, the dual AMD EPYC Turin system with Zen 5 CPUs was tested within Cinebench R23 and scored somewhere around 123K (~123,000) points. Compared to dual 96-core EPYC Genoa chips, the EPYC Turin 64-core chips are already faster than their predecessors in their ES state.

This is indeed an impressive showcase of AMD's Zen 5 CPUs but we have to remember that this is just a rumor for now. If this indeed turns out to be the case, then Zen 5 is going to be a complete beast and it should be since it is featuring architecture built from the ground up among a list of things. The outlet also states that while Zen 5 Turin will utilize 8-core CCDs, Zen 5C Turin-Dense is expected to utilize 16-core CCXs and that the company has a 3nm 16-core CCX in works though it should be remembered that AMD will have Zen 5 on both 4nm and 3nm nodes.

AMD Zen 5 in 2024, Featuring V-Cache & Compute Variants With Brand New Microarchitecture

AMD has so far confirmed that the new Zen 5 architecture will launch in 2024. The Zen 5 CPUs will come in three flavors (Zen 5 / Zen 5 V-Cache / Zen 5C) and the chip itself is designed from the ground up with a completely brand new microarchitecture that focuses on delivering enhanced performance and efficiency, a re-pipelined front-end, and wide issue along with Integrated AI and machine learning optimization. Some of the key features of Zen 5 CPUs include:

• Enhanced performance and efficiency
• Re-pipelined front end and wide issue
• Integrated AI and Machine Learning optimizations

AMD EPYC CPU Families:

Family Name	AMD EPYC Verano	AMD EPYC Venice	AMD EPYC Turin-X	AMD EPYC Turin-Dense	AMD EPYC Turin	AMD EPYC Siena	AMD EPYC Bergamo	AMD EPYC Genoa-X	AMD EPYC Genoa	AMD EPYC Milan-X	AMD EPYC Milan	AMD EPYC Rome	AMD EPYC Naples
Family Branding	EPYC 9007	EPYC 9006	EPYC 9005	EPYC 9005	EPYC 9005	EPYC 8004	EPYC 9004	EPYC 9004	EPYC 9004	EPYC 7004	EPYC 7003	EPYC 7002	EPYC 7001
Family Launch	2027	2026	2025	2025	2024	2023	2023	2023	2022	2022	2021	2019	2017
CPU Architecture	Zen 7	Zen 6	Zen 5	Zen 5C	Zen 5	Zen 4	Zen 4C	Zen 4 V-Cache	Zen 4	Zen 3	Zen 3	Zen 2	Zen 1
Process Node	TBD	2nm TSMC	4nm TSMC	3nm TSMC	4nm TSMC	5nm TSMC	4nm TSMC	5nm TSMC	5nm TSMC	7nm TSMC	7nm TSMC	7nm TSMC	14nm GloFo
Platform Name	SP7	SP7	SP5	SP5	SP5	SP6	SP5	SP5	SP5	SP3	SP3	SP3	SP3
Socket	TBD	TBD	LGA 6096 (SP5)	LGA 6096 (SP5)	LGA 6096	LGA 4844	LGA 6096	LGA 6096	LGA 6096	LGA 4094	LGA 4094	LGA 4094	LGA 4094
Max Core Count	TBD	96	128	192	128	64	128	96	96	64	64	64	32
Max Thread Count	TBD	192	256	384	256	128	256	192	192	128	128	128	64
Max L3 Cache	TBD	TBD	1536 MB	384 MB	384 MB	256 MB	256 MB	1152 MB	384 MB	768 MB	256 MB	256 MB	64 MB
Chiplet Design	TBD	8 CCD's (1 CCX per CCD) + 2 IOD?	16 CCD's (1CCX per CCD) + 1 IOD	12 CCD's (1CCX per CCD) + 1 IOD	16 CCD's (1CCX per CCD) + 1 IOD	8 CCD's (1CCX per CCD) + 1 IOD	12 CCD's (1 CCX per CCD) + 1 IOD	12 CCD's (1 CCX per CCD) + 1 IOD	12 CCD's (1 CCX per CCD) + 1 IOD	8 CCD's (1 CCX per CCD) + 1 IOD	8 CCD's (1 CCX per CCD) + 1 IOD	8 CCD's (2 CCX's per CCD) + 1 IOD	4 CCD's (2 CCX's per CCD)
Memory Support	TBD	DDR5-12800	DDR5-6000?	DDR5-6400	DDR5-6400	DDR5-5200	DDR5-5600	DDR5-4800	DDR5-4800	DDR4-3200	DDR4-3200	DDR4-3200	DDR4-2666
Memory Channels	TBD	16-Channel (SP7)	12 Channel (SP5)	12 Channel	12 Channel	6-Channel	12 Channel	12 Channel	12 Channel	8 Channel	8 Channel	8 Channel	8 Channel
PCIe Gen Support	TBD	128-192 PCIe Gen 6	TBD	128 PCIe Gen 5	128 PCIe Gen 5	96 Gen 5	128 Gen 5	128 Gen 5	128 Gen 5	128 Gen 4	128 Gen 4	128 Gen 4	64 Gen 3
TDP (Max)	TBD	~600W	500W (cTDP 600W)	500W (cTDP 450-500W)	400W (cDP 320-400W)	70-225W	320W (cTDP 400W)	400W	400W	280W	280W	280W	200W

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