AMD ‘Warhol’ Ryzen 5000 CPUs Will Succeed Vermeer On The TSMC 7nm Process
A rumor from twitter (@mebiuw via Videocardz) is making the rounds and contradicting the DigiTimes report from earlier today about AMD planning to skip directly top 5nm for Vermeer. While the tweet has since been deleted, it is from an account that has posted reliable leaks in the past and as such, could very well turn out to be true (historically, tweets that are deleted have a very high probability of being legitimate). By the way, mind that rumor tag and keep that lovable grain of salt handy.
AMD Ryzen 5000 Series CPUs Codenamed "Warhol": features PCIe 4, Zen 3 architecture and 7nm process
A recent report out of Taiwan caused quite the stir by stating that AMD was planning on making a surprise shift to TSMC's 5nm+ process in time for a launch at CES 2021. Such a move would absolutely upset the semiconductor industry and change the dynamics of silicon leadership completely as well. However, one of the regular leakers has released an AMD slide that appears to show that the company's Warhol based chips (that succeed Vermeer) are also based on 7nm with Raphael following on 5nm. If this is the case then the CES 2021 launch would probably be with 7nm chips and not 5nm.
Interestingly, not only do you learn that Warhol is the codename of the Ryzen 5000 series processors designed to succeed Vermeer but that Raphael is the codename for what I presume is the Ryzen 6000 series. It will be based on Zen 4 and feature TSMC's 5nm process. This also confirms that AMD has no intention of stopping its aggressive strategy with regards to node shifts.
The leaker also pointed out that the design rules of N7 are not the same as N5 so a surprise shift to 5nm might actually not be possible in this short a time span:
N5 doesn't share same desgin rules with N7P/+. Zen3 ES is N7P.
— MebiuW (@MebiuW) May 28, 2020
WikiChip mentions the roadmap of TSMC's process node and how they stack up to their predecessors:
TSMC 7nm (N7P)
- +7% Better Performance at same power versus N7
- 10% power savings at the same performance versus N7
TSMC 7nm (N7+)
- +10% Better Performance at same power versus N7
- 15% power savings at the same performance versus N7
TSMC 5nm (N5)
- +15% Better Performance at same power versus N7
- 30% power savings at the same performance versus N7
TSMC 5nm (N5P)
- +7% Better Performance at same power versus N5
- 15% power savings at the same performance versus N5
As you can see the transition from N7 to N5 is a huge one (the power saving is the dead give away) and this does not actually account for the density increases yet. Shifting to a lower process not only results in higher economies of scale but allows you to pack more transistors in the same space. That said, this leak contradicts DigiTimes report and says that Zen 3 engineering samples have already been fabricated on theN7P process. If this is the case, then it would be very hard to port it to N5 in a short amount of time. But it should be easy to port it to N7+ - which is the node based on EUV and will offer much higher clock rates and power savings.
[opinion] We very rarely see multiple leaks directly contradict each other in such a short time span and since both sources have proven to be reliable in the past I am not entirely sure what to make of this. Digitimes has a much larger history of accurate leaks but their claim is shocking to say the least, @MebiuW has a far less impressive track record but the evidence of the slides + the logic of the claims makes it very hard to pick a side here. [/opinion]
What do you think?
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