AMD's SP7 & SP8 platforms for the upcoming EPYC "Venice" & "Verano" CPUs have been detailed, and feature fast DDR5 & PCIe 6.0 support.
AMD To Take Server IO To The Next-Level With SP7 & SP8 Platforms, Powered By Next-Gen EPYC "Venice" and "Verano" CPUs
Just a few hours ago, AMD announced its EPYC Venice and EPYC Verano CPUs. The former comes with up to 256 cores in Zen 6C flavors with a launch scheduled for 2026, while the latter seems to either be an improvement of the Zen 6 or a fresh Zen 7 chip, slated for a 2027 launch. Now, while AMD is sharing only tidbits, it looks like leakers have revealed what we can expect from these next-generation platforms.
Starting first with the SP7 platform, it looks like AMD is going big with up to 16-channel DDR5 DRAM support that will feature up to 8000 MT/s ECC and 12,800 MT/s MRDIMMs in 1DPC configurations. It will also come with support for 1, 4, 8, 16, and 16-channel memory interleaves, and the types of memory supported by the platform will be expanded with RDIMM, 3DS RDIMM, MRDIMM, and Tall DIMM Dram solutions.
On the I/O side, the AMD SP7 platform will retain 2P support, so that's two next-gen sockets per motherboard and up to 128 PCIe Gen 6.0 lanes, offering 64 Gbps of bandwidth per lane. The SP7 platform will also offer up to 16 "Bonus" PCIe Gen 4 lanes. The single-socket "1P" version will get up to 96 PCIe Gen 6.0 lanes and 8 additional PCIe Gen 4 lanes. The platform will also support SDCI or Smart Data Cache Injection.
Summing up the platform, you are getting the following on AMD's SP7:
- Up To 16-Channel DDR5 Support
- Up To 8000 MT/s DDR5 ECC Memory
- Up To 12800 MT/s DDR5 RDIMM Memory
- Support for RDIMM, 3DS RDIMM, MRDIMM, Tall DIMM
- Up To 128 PCI Gen 6 + 16 PCIe Gen 4 Lanes on 2P Platform
- Up To 96 PCIe Gen 6 + 8 PCIe Gen 4 Lanes on 1P Platform
While the SP7 platform is meant for high-end enterprise and data center markets, SP8 will serve as the entry-level platform solution while retaining support for next-gen EPYC chips. The platform will retain the same memory compatibility, but in 8-channel configurations. Interestingly, SP8 will offer more Gen 6.0 lanes versus SP7, with up to 192 PCIe Gen 6.0 lanes on 2P and 128 PCIe Gen 6.0 lanes on 1P platforms.
Summing up the platform, you are getting the following on AMD's SP8:
- Up To 8-Channel DDR5 Support
- Up To 8000 MT/s DDR5 ECC Memory
- Up To 12800 MT/s DDR5 RDIMM Memory
- Support for RDIMM, 3DS RDIMM, MRDIMM, Tall DIMM
- Up To 192 PCI Gen 6 + 16 PCIe Gen 4 Lanes on 2P Platform
- Up To 128 PCIe Gen 6 + 8 PCIe Gen 4 Lanes on 1P Platform
We also have a slight glimpse of how the CPU configurations will be arranged for the next-gen line. The Zen 6C or Zen 6 Dense chips will offer up to 32 cores per CCD, and there are a total of 8 CCDs, so that rounds up to the 256 core count figure which AMD presented during its keynote. Each CCD will pack 128 MB of L3 cache for a total of 1024 or 1 GB of L3 cache on the full chip.
There are also two IO dies on the chip, with each featuring PCIe Gen 6.0 / CXL 3.1 functionality, and support for DDR5-8000 memory (interestingly, the diagram here lists the maximum MRDIMM speeds at 10,400 MT/s versus the 12,800 MT/s listed above), Gen4 Infinity Fabric, and Secure Processor.
The standard AMD EPYC "Venice" CPUs based on the classic Zen 6 cores will feature 12 cores per CCD, and the diagram shows eight CCDs with the same dual IO die configuration. These round up to 96 cores and 192 threads, so the same core count as the existing Turin offerings. Each CCD will get 48 MB of L3 cache, which is a 50% increase over the 32 MB L3 featured on Zen 5 chips.
- EPYC 9006 "Venice" With Zen 6C: 256 Cores / 512 Threads / Up To 8 CCDs / 1024 MB L3
- EPYC 9005 "Turin" With Zen 5C: 192 Cores / 384 Threads / Up To 12 CCDs / 384 MB L3
- EPYC 9006 "Venice" With Zen 5: 96 Cores / 192 Threads / Up To 8 CCDs / 384 MB L3
- EPYC 9005 "Turin" With Zen 5: 96 Cores / 192 Threads / Up To 16 CCDs / 384 MB L3
As per previous reports, the EPYC SP7 variants will feature TDPs of around 600W, up from 400W on Zen 5, and the SP8 chips will feature TDPs between 350- 400W. It should look like the following:
That about sums up this leak. AMD is upping its core count, compute capability, and IO features once again in a fantastic fashion. With EPYC Venice CPUs coming in 2026 and followed by the next-gen Verano in 2027, we are in for exciting times for the data center segment.
AMD EPYC CPU Families:
| Family Name | AMD EPYC Verano | AMD EPYC Venice | AMD EPYC Turin-X | AMD EPYC Turin-Dense | AMD EPYC Turin | AMD EPYC Siena | AMD EPYC Bergamo | AMD EPYC Genoa-X | AMD EPYC Genoa | AMD EPYC Milan-X | AMD EPYC Milan | AMD EPYC Rome | AMD EPYC Naples |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Family Branding | EPYC 9007 | EPYC 9006 | EPYC 9005 | EPYC 9005 | EPYC 9005 | EPYC 8004 | EPYC 9004 | EPYC 9004 | EPYC 9004 | EPYC 7004 | EPYC 7003 | EPYC 7002 | EPYC 7001 |
| Family Launch | 2027 | 2026 | 2025 | 2025 | 2024 | 2023 | 2023 | 2023 | 2022 | 2022 | 2021 | 2019 | 2017 |
| CPU Architecture | Zen 7 | Zen 6 | Zen 5 | Zen 5C | Zen 5 | Zen 4 | Zen 4C | Zen 4 V-Cache | Zen 4 | Zen 3 | Zen 3 | Zen 2 | Zen 1 |
| Process Node | TBD | 2nm TSMC | 4nm TSMC | 3nm TSMC | 4nm TSMC | 5nm TSMC | 4nm TSMC | 5nm TSMC | 5nm TSMC | 7nm TSMC | 7nm TSMC | 7nm TSMC | 14nm GloFo |
| Platform Name | SP7 | SP7 | SP5 | SP5 | SP5 | SP6 | SP5 | SP5 | SP5 | SP3 | SP3 | SP3 | SP3 |
| Socket | TBD | TBD | LGA 6096 (SP5) | LGA 6096 (SP5) | LGA 6096 | LGA 4844 | LGA 6096 | LGA 6096 | LGA 6096 | LGA 4094 | LGA 4094 | LGA 4094 | LGA 4094 |
| Max Core Count | TBD | 96 | 128 | 192 | 128 | 64 | 128 | 96 | 96 | 64 | 64 | 64 | 32 |
| Max Thread Count | TBD | 192 | 256 | 384 | 256 | 128 | 256 | 192 | 192 | 128 | 128 | 128 | 64 |
| Max L3 Cache | TBD | TBD | 1536 MB | 384 MB | 384 MB | 256 MB | 256 MB | 1152 MB | 384 MB | 768 MB | 256 MB | 256 MB | 64 MB |
| Chiplet Design | TBD | 8 CCD's (1 CCX per CCD) + 2 IOD? | 16 CCD's (1CCX per CCD) + 1 IOD | 12 CCD's (1CCX per CCD) + 1 IOD | 16 CCD's (1CCX per CCD) + 1 IOD | 8 CCD's (1CCX per CCD) + 1 IOD | 12 CCD's (1 CCX per CCD) + 1 IOD | 12 CCD's (1 CCX per CCD) + 1 IOD | 12 CCD's (1 CCX per CCD) + 1 IOD | 8 CCD's (1 CCX per CCD) + 1 IOD | 8 CCD's (1 CCX per CCD) + 1 IOD | 8 CCD's (2 CCX's per CCD) + 1 IOD | 4 CCD's (2 CCX's per CCD) |
| Memory Support | TBD | DDR5-12800 | DDR5-6000? | DDR5-6400 | DDR5-6400 | DDR5-5200 | DDR5-5600 | DDR5-4800 | DDR5-4800 | DDR4-3200 | DDR4-3200 | DDR4-3200 | DDR4-2666 |
| Memory Channels | TBD | 16-Channel (SP7) | 12 Channel (SP5) | 12 Channel | 12 Channel | 6-Channel | 12 Channel | 12 Channel | 12 Channel | 8 Channel | 8 Channel | 8 Channel | 8 Channel |
| PCIe Gen Support | TBD | 128-192 PCIe Gen 6 | TBD | 128 PCIe Gen 5 | 128 PCIe Gen 5 | 96 Gen 5 | 128 Gen 5 | 128 Gen 5 | 128 Gen 5 | 128 Gen 4 | 128 Gen 4 | 128 Gen 4 | 64 Gen 3 |
| TDP (Max) | TBD | ~600W | 500W (cTDP 600W) | 500W (cTDP 450-500W) | 400W (cDP 320-400W) | 70-225W | 320W (cTDP 400W) | 400W | 400W | 280W | 280W | 280W | 200W |
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