AMD EPYC Verano “Highest Frequency” & Venice-X “3D V-Cache” CPUs Launch Next Year, Tackling Agentic AI & HPC-Oriented Workloads With Zen 6

AMD has confirmed that its EPYC Verano and 3D V-Cache boosted Venice-X CPUs will launch next year as Zen 6 tackles a broad range of HPC & AI workloads.

AMD Verano Couples High-Frequency Zen 6 With Efficiency-Optimized LPDDR Memory While Venice-X Tackles HPC With 3D V-Cache Boost

Today at Advancing AI 2026, AMD confirmed that its EPYC CPU lineup will be expanded next year with even more options aimed at AI and HPC workloads. The two brand new chips for 2027 are EPYC Verano and EPYC Venice-X.

Microsoft already spilled the beans on the AMD Venice-X chips, which will be deployed within its Azure HXv2 instances next year. The chips will feature up to 96 cores and 192 threads, with 2P platforms offering up to 192 "Zen 6" cores, 384 threads, over 5 GHz clock speeds (5.15 GHz max), and 50% more addressable cache per core as the 3D V-Cache stacks sit beneath the Zen 6 cores to offer increased technical compute and HPC capabilities.

These chips will carry an impressive 1152 MB of L3 cache, and will support both DDR5-8000 & the industry's fastest MRDIMM's with up to 12,800 MT/s speeds across 16 channels.

Verano Is Purpose-Built For Agents

The AMD EPYC Verano CPUs are built on the same Zen 6 core architecture and are part of the EPYC 9006 "LP" family. These chips will feature up to 72 cores and 144 threads, up to 112 Gbps xGMI connectivity speeds to feed Instinct MI500 GPUs in next-gen AI racks for Agentic workloads.

AMD's EPYC Verano CPUs will be the first to support SOCAMM2 memory. SOCAMM2 is a relatively new memory form factor that currently harnesses LPDDR5X DRAM modules and offers high bandwidth, high capacity, and much better power efficiency in a compact form factor. This allows tech vendors to ensure maximum memory density. Verano "LP" CPUs will be configured on the SP8 platform.

For example, Micron recently shipped SOCAMM2 modules to various partners working on infrastructure for AI. These modules house 256 GB densities and are specifically targeted towards AI at scale. NVIDIA's Vera CPU solution features 16 of these modules with four LPDDR5X modules each for a total of 64 DRAM packages.

Like AMD, NVIDIA's next-gen Vera Rubin and Vera CPX platforms also feature SOCAMM2 LPDDR5X memory. And LPDDR is also the prime choice of several upcoming AI accelerators, such as Tesla's A15, which was recently revealed, and also several Intel inference-optimized GPU solutions.

This worsens the already-worse situation for LPDDR since the overall memory supply chain is tight, and the constraints aren't seeing any sign of relief. With more dense solutions rolling out in the future, it is not only going to affect server and PC audiences, but low-power DDR memory is also a vital component for smartphones, and with a large supply heading to AI racks, this could further disrupt the tech industry as a whole.

AMD EPYC CPU Families:

Family Name	AMD EPYC Verano	AMD EPYC Venice-Dense	AMD EPYC Venice	AMD EPYC Turin-X	AMD EPYC Turin-Dense	AMD EPYC Turin	AMD EPYC Siena	AMD EPYC Bergamo	AMD EPYC Genoa-X	AMD EPYC Genoa	AMD EPYC Milan-X	AMD EPYC Milan	AMD EPYC Rome	AMD EPYC Naples
Family Branding	EPYC 9007	EPYC 9006	EPYC 9006	EPYC 9005	EPYC 9005	EPYC 9005	EPYC 8004	EPYC 9004	EPYC 9004	EPYC 9004	EPYC 7004	EPYC 7003	EPYC 7002	EPYC 7001
Family Launch	2027	2026	2026	2025	2025	2024	2023	2023	2023	2022	2022	2021	2019	2017
CPU Architecture	Zen 6+	Zen 6C	Zen 6	Zen 5	Zen 5C	Zen 5	Zen 4	Zen 4C	Zen 4 V-Cache	Zen 4	Zen 3	Zen 3	Zen 2	Zen 1
Process Node	TBD	2nm TSMC	2nm TSMC	4nm TSMC	3nm TSMC	4nm TSMC	5nm TSMC	4nm TSMC	5nm TSMC	5nm TSMC	7nm TSMC	7nm TSMC	7nm TSMC	14nm GloFo
Platform Name	SP7	SP7	SP7	SP5	SP5	SP5	SP6	SP5	SP5	SP5	SP3	SP3	SP3	SP3
Socket	TBD	TBD	TBD	LGA 6096 (SP5)	LGA 6096 (SP5)	LGA 6096	LGA 4844	LGA 6096	LGA 6096	LGA 6096	LGA 4094	LGA 4094	LGA 4094	LGA 4094
Max Core Count	TBD	256	96	128	192	128	64	128	96	96	64	64	64	32
Max Thread Count	TBD	512	192	256	384	256	128	256	192	192	128	128	128	64
Max L3 Cache	TBD	1024 MB? (128 MB /CCD)	384 MB? (48 MB/CCD)	1536 MB	384 MB	384 MB	256 MB	256 MB	1152 MB	384 MB	768 MB	256 MB	256 MB	64 MB
Chiplet Design	TBD	8 CCD's (1 CCX per CCD) + 2 IOD?	8 CCD's (1 CCX per CCD) + 2 IOD	16 CCD's (1CCX per CCD) + 1 IOD	12 CCD's (1CCX per CCD) + 1 IOD	16 CCD's (1CCX per CCD) + 1 IOD	8 CCD's (1CCX per CCD) + 1 IOD	12 CCD's (1 CCX per CCD) + 1 IOD	12 CCD's (1 CCX per CCD) + 1 IOD	12 CCD's (1 CCX per CCD) + 1 IOD	8 CCD's (1 CCX per CCD) + 1 IOD	8 CCD's (1 CCX per CCD) + 1 IOD	8 CCD's (2 CCX's per CCD) + 1 IOD	4 CCD's (2 CCX's per CCD)
Memory Support	TBD	DDR5-8000+	DDR5-8000+	DDR5-6400	DDR5-6400	DDR5-6400	DDR5-5200	DDR5-5600	DDR5-4800	DDR5-4800	DDR4-3200	DDR4-3200	DDR4-3200	DDR4-2666
Memory Channels	TBD	16-Channel (SP7)	16-Channel (SP7)	12 Channel (SP5)	12 Channel	12 Channel	6-Channel	12 Channel	12 Channel	12 Channel	8 Channel	8 Channel	8 Channel	8 Channel
PCIe Gen Support	TBD	128-192 PCIe Gen 6	128-192 PCIe Gen 6	TBD	128 PCIe Gen 5	128 PCIe Gen 5	96 Gen 5	128 Gen 5	128 Gen 5	128 Gen 5	128 Gen 4	128 Gen 4	128 Gen 4	64 Gen 3
TDP (Max)	TBD	~600W	~600W	500W (cTDP 600W)	500W (cTDP 450-500W)	400W (cDP 320-400W)	70-225W	320W (cTDP 400W)	400W	400W	280W	280W	280W	200W

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