AMD EPYC Roadmap Confirms Zen 4 Powered Genoa-X & Siena & Zen 5 Powered Turin Server CPU Families
AMD also shed a light on its EPYC CPU roadmap which now includes the next-gen Genoa-X, Siena Zen 4, and Turing Zen 5 families.
AMD EPYC Roadmap Adds Zen 4 Powered Genoa-X 'V-Cache' & Siena, Zen 5 Powered Turin Server CPU Families
The latest roadmap was presented by Dan McNamara, AMD's Senior Vice President and General Manager of Server. The EPYC roadmap confirmed that AMD is working on four diverse EPYC CPU families based on the Zen 4 core architecture while also confirming the next-generation Zen 5-powered family, codenamed Turing.
AMD Zen 4 Family Gets Genoa, Genoa-X, Bergamo and Siena EPYC CPU Families
AMD wants to focus on the SP5 platform which is based around the LGA 6096 socket and will feature three generations of processor lineups, Genoa, Genoa-X, and Bergamo. The AMD EPYC Genoa CPUs will feature up to 96 Zen 4 cores in 200-400W SKUs while Bergamo will feature a total of 128 Zen 4 cores in 320-400W SKUs. The SP5 platform is a high-end design that offers both 1P & 2P support, up to 12-Channel DDR5 memory, up to 160 PCIe Gen 5.0 lanes, and 64 Lanes for CXL V1.1+, and up to 12 PCIe Gen 3.0 lanes.
AMD EPYC Genoa CPUs - 5nm Zen 4 & Up To 96 Cores In 2022
Starting with the details, AMD has already announced that EPYC Genoa would be compatible with the new SP5 platform which brings a new socket so SP3 compatibility would exist up till EPYC Milan. The EPYC Genoa processors would also feature support for new memory and new capabilities. In the latest details, it is reported that the SP5 platform will also feature a brand new socket that will feature 6096 pins arranged in the LGA (Land Grid Array) format. This will be by far the biggest socket that AMD has ever designed with 2002 more pins than the existing LGA 4094 socket.
AMD EPYC Milan Zen 3 vs EPYC Genoa Zen 4 Size Comparisons:
|CPU Name||AMD EPYC Milan||AMD EPYC Genoa|
|Process Node||TSMC 7nm||TSMC 5nm|
|Core Architecture||Zen 3||Zen 4|
|Zen CCD Die Size||80mm2||72mm2|
|Zen IOD Die Size||416mm2||397mm2|
|Substrate (Package) Area||TBD||5428mm2|
|Socket Name||LGA 4094||LGA 6096|
|Max Socket TDP||450W||700W|
The socket will support AMD's EPYC Genoa and future generations of EPYC chips. Talking about Genoa CPUs themselves, the chips will pack a mammoth 96 cores and 192 threads. These will be based on AMD's brand new Zen 4 core architecture which is expected to deliver some insane IPC uplifts while utilizing the TSMC 5nm process node.
To get to 96 cores, AMD has to pack more cores in its EPYC Genoa CPU package. AMD is said to achieve this by incorporating a total of up to 12 CCD's in its Genoa chip. Each CCD will feature 8 cores based on the Zen 4 architecture. That aligns with the increased socket size and we could be looking at a massive CPU interposer, even larger than the existing EPYC CPUs. The CPU is said to feature TDPs of 320W which will be configurable up to 400W. You can find more details regarding the SP5 platform here.
Other than that, it is stated that AMD's EPYC Genoa CPUs will feature 128 PCIe Gen 5.0 lanes, 160 for a 2P (dual-socket) configuration. The SP5 platform will also feature DDR5-5200 memory support which is some insane improvement over the existing DDR4-3200 MHz DIMMs. But that's not all, it will also support up to 12 DDR5 memory channels and 2 DIMMs per channel which will allow up to 3 TB of system memory using 128 GB modules.
AMD EPYC Bergamo CPUs - 5nm Zen 4 & Up To 128 Cores
The EPYC Bergamo chips will be featuring up to 128 cores and will be aiming at the HBM-powered Xeon chips along with server products from Apple and Google with higher core counts (ARM architecture). Both Genoa and Bergamo will utilize the same SP5 socket and the main difference is that Genoa is optimized for higher clocks while Bergamo is optimized around higher-throughput workloads.
The AMD EPYC Genoa chip renders revealed a total of 12 Zen 4 CCD's to reach 96 cores so a total of 16 Zen 4 CCD's will be required for Bergamo to hit its 128 core count. The final die arrangement is definitely going to be an interesting sight and there are several rendered revisions from a series of leaks.
The Genoa-X CPUs are expected to hit production by end of Q3 / early Q1 2023 and will launch around mid of 2023. They will feature a similar design methodology as the Milan-X chips with 3D V-Cache as 'Large L3' is a highlighted feature of the lineup. While Milan-X features up to 768 MB of L3 cache, Genoa-X CPUs will feature over 1 GB of L3 cache while rocking the same 96 cores based on the Zen 4 design. So in total, SP5 will end up with three EPYC families.
What's SP6? A Cost-Optimized Version of SP5 For Edge Servers
At the same time, AMD is expected to introduce a new platform known as SP6 which will be a more TCO-optimized offering for low-end servers. It will be a 1P solution, offering 6-channel memory, 96 PCIe Gen 5.0 lanes, 48 lanes for CXL V1.1+, and 8 PCIe Gen 3.0 lanes. The platform will feature Zen 4 EPYC CPUs but only the entry-level solutions with up to 32 Zen 4 and up to 64 Zen 4C cores under the EPYC Siena family.
Their TDPs will range between 70-225W. So it looks like the SP6 platform is designed to support the entry-level variants of EPYC Genoa, Bergamo, and even Turin CPUs. It will focus on Density & Perf/Watt optimizations for Edge / Telecommunication segment leadership.
In documentation discovered by @Olrak (via Anandtech Forums), it looks like the SP6 socket is vastly similar to the existing SP3 socket so the packaging layout of the SP6 chips will be similar compared to existing EPYC CPUs too. They won't use the full 12-die layout as Bergamo does but rather stick to an 8-die layout as the existing parts. While the socket looks the same, the internal pin layout has been modified to LGA 4844 vs LGA 4096 (on SP3 sockets). Other measurements are the same at 58.5 x 75.4.
The majority of the AMD EPYC Zen 4 families will be available in 2023 while Zen 5 'EPYC Turin' is planned to launch by 2024.
AMD EPYC CPU Families:
|Family Name||AMD EPYC Venice||AMD EPYC Turin||AMD EPYC Siena||AMD EPYC Bergamo||AMD EPYC Genoa-X||AMD EPYC Genoa||AMD EPYC Milan-X||AMD EPYC Milan||AMD EPYC Rome||AMD EPYC Naples|
|Family Branding||EPYC 7007?||EPYC 7006?||EPYC 7004?||EPYC 7005?||EPYC 7004?||EPYC 7004?||EPYC 7003X?||EPYC 7003||EPYC 7002||EPYC 7001|
|CPU Architecture||Zen 6?||Zen 5||Zen 4||Zen 4C||Zen 4 V-Cache||Zen 4||Zen 3||Zen 3||Zen 2||Zen 1|
|Process Node||TBD||3nm TSMC?||5nm TSMC||5nm TSMC||5nm TSMC||5nm TSMC||7nm TSMC||7nm TSMC||7nm TSMC||14nm GloFo|
|Platform Name||TBD||SP5 / SP6||SP6||SP5||SP5||SP5||SP3||SP3||SP3||SP3|
|Socket||TBD||LGA 6096 (SP5)|
LGA XXXX (SP6)
|LGA 4844||LGA 6096||LGA 6096||LGA 6096||LGA 4094||LGA 4094||LGA 4094||LGA 4094|
|Max Core Count||384?||256||64||128||96||96||64||64||64||32|
|Max Thread Count||768?||512||128||256||192||192||128||128||128||64|
|Max L3 Cache||TBD||TBD||256 MB?||TBD||1152 MB?||384 MB?||768 MB?||256 MB||256 MB||64 MB|
|Chiplet Design||TBD||TBD||8 CCD's (1CCX per CCD) + 1 IOD||12 CCD's (1 CCX per CCD) + 1 IOD||12 CCD's (1 CCX per CCD) + 1 IOD||12 CCD's (1 CCX per CCD) + 1 IOD||8 CCD's with 3D V-Cache (1 CCX per CCD) + 1 IOD||8 CCD's (1 CCX per CCD) + 1 IOD||8 CCD's (2 CCX's per CCD) + 1 IOD||4 CCD's (2 CCX's per CCD)|
|Memory Channels||TBD||12 Channel (SP5)|
|6-Channel||12 Channel||12 Channel||12 Channel||8 Channel||8 Channel||8 Channel||8 Channel|
|PCIe Gen Support||TBD||TBD||96 Gen 5||160 Gen 5||160 Gen 5||160 Gen 5||128 Gen 4||128 Gen 4||128 Gen 4||64 Gen 3|
|TDP Range||TBD||480W (cTDP 600W)||70-225W||320W (cTDP 400W)||200W (cTDP 400W)||200W (cTDP 400W)||280W||280W||280W||200W|