AMD Carrizo Technical Slides – New GPU, Highly Power Efficient Architecture and HDL
AMD recently unveiled the official technical slides (via SemiAccurate) on Carrizo APU (something that was leaked a few days back already) and I thought it would be a good idea to go over some of the final details hidden in the technical showcase. Important design features such as the new High Density Library design were showcased - something found commonly in GPU architecture. The integrated-GPU is newer than the one featured on "Kaveri." It features 8 compute units (512 stream processors) based on Graphics CoreNext 1.3 architecture, with Mantle and DirectX 12 API support, and H.265 hardware-acceleration.
High Density Libraries, AVFS, More efficient GPU and More in Carrizo
AMD's architecture is very modular in nature. To quote themselves, it's built like lego. They can combine different cores to create different products almost seamlessly and easily. Everything is built from the scratch up to have multiple configurations and mixing. This allows them to have a very dynamic roadmap - and also highly susceptible to change - giving them the freedom of being able to react to Industry as well. Keeping that in mind the new HDL (High Density Library ) feature of Carrizo is something that should have micro-architecture enthusiasts pretty excited about. Carrizo integrates the Southbridge on the SoC favoring single chip design to an MCM. Not to mention that the slides also show the Soi3 state indicating that the processor will be capable of advanced power saving functions. It goes without saying that Intel's implementation is superior but the Soi3 state allows AMD to approach the same level.
An interesting query now arises. The current design actually makes the CPU a bit more GPU like than tradition. Apparently, the inverse could hold true for the GPU as well. The transistor choice states the same thing. I have a feeling we are looking at an architecture that was designed for the ground up to support HSA. HSA is about a unified chip working exploiting parallel loads and this sounds like the perfect mixup to do just that. AMD has also employed something called Voltage Adaptive Operation or AVFS which can allegedly reduce power consumption by around 19% for the CPU and 10% for the GPU. Interestingly the concept of vdroop is relevant here. For those who donot know, vdroop is the calibrated feature of a die to reduce voltage supplied at a frequency jump to avoid over powering the core and accidentally supplying more current. Overclockers counter the feature by using something called Load Line Calibration and this new feature appears to be an advanced implementation of the same.
Lets talk HDL now, simply put, HDL is packing more metal layers in the same die area. Something that is not only extensively used in GPU production but pretty common in the top silicon players. AMD's Carrizo APU uses eight layers. The downside of compressing layers is that the upper limit (or OC headroom) at higher clocks will be limited due to the confined space while offering more power efficiency at lower clocks - and considering Carrizo targets the mobile segment, that is perfectly fine. It also means that Excavator is significantly more power efficient while packing a smaller foot print at the same time - now that's good architectural improvement.
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