AMD has published a new patent in which the company talks about an active chiplet serving as a bridge between multiple GPU dies, possibly based on its next-generation RDNA 3 architecture for GPUs and APUs.
AMD Active Bridge Chiplet Patent Might Give Us A Glimpse of The Next-Gen RDNA 3 Graphics Architecture Based GPUs and APUs
The patent starts off by stating the elephant in the room and that's conventional monolithic GPU designs. We all know how well chiplets worked out for AMD in the CPU segment & the company is now planning to follow the same route on the GPU side. It's no surprise that AMD's rival, NVIDIA, is also investing in MCM designs that will be utilized in its next-generation GPUs. It also makes sense because as of right now, process technology advancement is a crucial factor and you can't reduce the size of GPUs as much as back in the old days considering just how much different IPs a singular GPU packs these days.
AMD's solution is to invest in chiplet designs for its next-generation GPU architectures. We can say that this is our first look at the RDNA 3 architecture or a future variant of RDNA. AMD does state it faces a problem in making multiple GPUs work in parallel, think of Crossfire which is a redundant technology as are all multi-GPU implementations. To fix this problem and make the programming model work for chiplet, AMD has proposed an active bridge chiplet that would bridge multiple GPU chiplets together.
The main block diagram of the conceptual design shows a chip featuring multiple chiplets. The CPU portion is connected to the first GPU chiplet via a communication bus (future generation of Infinity Fabric) while the GPU chiplets are interconnected via the active bridge chiplet. This is an on-die bus interface that connects an n-number of GPU chiplets. What's more interesting is that the bridge will also feature an L3 LLC (Last Level Cache) which is coherent and unified across the multiple chiplets, reducing cache bottlenecks. The AMD Active Bridge Chiplet hence allows for the parallel working of the chiplets on existing programming models and reduces the need for having separate L3 caches for each GPU chiplet.
FIG. 2 is a block diagram illustrating a sectional view of GPU chiplets and passive crosslinks in accordance with some embodiments.
FIG. 3 is a block diagram illustrating a cache hierarchy of GPU chiplets coupled by a passive crosslink in accordance with some embodiments.
FIG. 4 is a block diagram illustrating a floor plan view of a GPU chiplet in accordance with some embodiments.
FIG. 5 is a block diagram illustrating a processing system utilizing a four-chiplet configuration in accordance with some embodiments.
Currently, the block diagram talks about an SOC design which hints that this might be a design for future AMD RDNA 3 based APUs for mobility, desktop platforms, and consoles however, we should also expect a similar implementation on discrete GPUs for desktop-grade graphics cards and future HPC products based on the CDNA 2 & CDNA 3 architectures. It will be interesting to see this tech work on future AMD Radeon and Instinct GPUs.
Currently, AMD features Infinity Fabric and Infinity Cache solutions on its existing RDNA 2 line of graphics chips so one can expect a naming scheme like Infinity Bridge for this solution once it's launched.