AMD Carrizo APU on the 28nm Node Will Have Stacked DRAM On Package – Alleges Italian Leak

Hardware 4 months ago by
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[RUMOR] Notice the shiny tag at the start. Continue. We have received some information regarding AMD’s upcoming APU Carrizo, this information is unverified so I will be treating it as a rumor. The report comes from the Italian site bitsandchips.it and states that AMD’s upcoming flagship APUs will have Stacked DRAM while maintaining the 28nm Node.

Carrizo APU RoadmapThe Quite Old ‘Leaked’ Roadmap

Carrizo APU will be based on the 28nm Node and have HBM (High Bandwidth Memory)

Now it goes without saying, that you need to keep that pinch of salt handy throughout this post. However this news, if true, is very interesting. We know for a fact that APUS benefit a lot from good memory and if these APUs will truly support HBM then we can expect to see some very substantial performance per clock gains while jumping from Kaveri to Carrizo even while staying on the same node. Another important point to note is that with the Carrizo APU the implementation of HSA will be perfected resulting in probably significant in compute as well as gaming.

Now we already know that AMD is working with Hynix to create Stacked DRAM.  We also know that this memory will come in two types, namely 3DS and HBM (Don’t be fooled by the lack of 3D in this name, both are stacked). The memory that is in question here is the HBM variant type which will feature the highest bandwidth and I know for a fact that there are two types already in production. Namely the 2-Hi and 4-Hi variants. You can find the detailed analysis of the same in my Pascal Architecture Analysis. Now the max bandwidth of a single HBM is 128-256 GBps (compare this to the 28GBps of GDDR5), so we are looking at an insane growth in bandwidth, albeit at reduced clocks (most probably around 1000Mhz).

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WCCFTech GDDR5 2-Hi HBM ‘Stacked DRAM’ 4-Hi HBM ‘Stacked DRAM’
I/O 32 512 1024
Max Bandwidth Per Pin 7 Gbps 1 Gbps 1 Gbps
Max Bandwidth 28 GBps 64 GBps 128 GBps
Voltage 1.35 – 1.65 ~1.2 ~1.2
Command Input Single Dual Dual
Layers 1 2 + 1 4 + 1

Now we previously received a much more authentic report that the APU would actually feature DDR4 support but this is obviously better. Carrizo APU’s die size will be smaller than Kaveri APU according to the same source, though I am not sure how they aim to accomplish this if the HBM is truly “on-package”. The Stacked DRAM will be manufactured on the 20nm node but the APU will stay at 28nm. Previous leaks had suggested that the upcoming APU will be compatible with the FM2+ socket and have TDP no greater than 65W. However the thing is, the last authentic leak was quite a while back and AMD’s plans could have changed in the meantime. We will be waiting for more information on this front and in the meantime this should serve as good food for thought, if nothing else.

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