Western Digital has added two new processor cores, the SweRV Core EH2 and the SweRV Core EL2, into its SweRV portfolio of microcontroller CPUs. The current processor core, the SweRV Core EH1, is based on 28nm and has just one thread running at 4.9 MHz. The SweRV Core EH1 uses the RISC-V Type of RV32IMC and has a 9-dual pipeline stage while the two newer cores will be built on the 16 nm processor nodes.
The newer Western Digital SweRV cores plan to significantly increase the processing power over the current RISC-V cores on the market!
Western Digital's SweRV cores have three different models of the cores SweRV Core EH1, SweRV Core EH2, and SweRV Core EL2, which all offer different specifications. The two newer cores are the SweRV Core EH2 and the SweRV Core EL2, and the SweRV Core EH2 uses the same 9-dual pipeline stage that the SweRV Core EH1 uses but instead of having one thread per core the SweRV Core EH2 has two 16-nm cores that run amazingly fast running at the speed of 6.3 MHz.
The SweRV Core EH2 has two threads and focus on splitting the information between the two cored, but the fetch 1, fetch 2, align, and decode are not divided between two separate threads.
The SweRV Core EL2 is designed around the idea of minimization as these cores will be used to replace the SoCs controller to make these cores as small as possible. This core focuses on a 1-way scalar design and a four-stage pipeline, which is planned to decrease the overall size of the core significantly.
The much higher core clock allows for potentially much faster hard drives. Western Digital does state that all of these cores will be used in a variety of its products "in the near future" but doesn't tell when they will start appearing in products or what products they will appear in. This variety of cores will help further enrich the RISC-V ecosystem in general.
Western digital has shown its first hardware reference for its OmniXtend cache coherent memory over Ethernet-compatible fabric protocol. This hardware reference shows how Wester Digitial plans to accelerate hard drive by using higher-end microcontrollers. This system could be used for adding persistent memory to CPUs, but it could also be integrated into components like GPUs and machine learning accelerators. The design has been made available, and the Chip Alliance will handle further development of the OmniXtend protocol.