TSMC is facing a surge in AI chip orders using its advanced packaging technology, such as CoWoS, but competitors such as Intel are benefiting as the Taiwanese semiconductor powerhouse is unable to keep up with demand.
Intel & Other Advanced Packaging Chip Manufacturers See Surge In Orders From TSMC Customers As CoWoS Unable To Meet Industry Demand
AI and HPC chip demand has reached an unprecedented level, and the chips that are being built are based on some of the most advanced packaging technologies that the world has ever seen.
Leading this advanced packaging race is none other than TSMC, whose CoWoS (Chip-on-Wafer-on-Substrate) had a head start over the competition and has been the go-to choice for several years. As demand shoots through the roof, even the Taiwanese giant is facing the brunt of existing bottlenecks within the supply chain and is unable to meet demand.
Not just that, competition is growing at an unprecedented pace. Intel is aiming to become the 2nd largest advanced packaging provider with its EMIB technologies that are poised to offer several benefits over CoWoS. Furthermore, a wave of Taiwanese packaging and test companies, namely ASE, SPIL, Powertech, and KYEC, is also taking advantage of the situation as TSMC orders face a spill-over effect.
The current situation for TSMC may be beneficial from a revenue/profit point of view, but given that it is the main producer of chips for NVIDIA and customers are already reserving capacity that hasn't even been built in advance, it makes things even tougher for the company. Other major AI and HPC customers of TSMC include AMD, Amazon AWS, and many more.
Reports indicate that Intel, with active support from the US government, is aggressively pursuing advanced packaging, and Taiwanese packaging and testing companies, including ASE, SPIL, Powertech, and KYEC, are also taking advantage of the spillover effect of orders.
NVIDIA's surging chip orders are a big profit boost for the company as millions of these chips are expected to power the global AI landscape, and wafer prices have already gone up sharply.
AMD is already using TSMC's CoWoS to produce its next-gen EPYC Venice chips on the N2P node, which is in volume production, and will also utilize TSMC's advanced packaging technologies for its upcoming MI400 and MI500 chips, with millions of these chips expected to land across multiple Frontier-Scale & Hyperscaler platforms.
Currently, TSMC operates a total of five advanced packaging and testing plants in Taiwan, which include locations at Hsinchu Science Park, Southern Taiwan Science Park, Taoyuan Longtan, Central Taiwan Science Park, and Miaoli Zhunan. The company is already building several other facilities in Taiwan to boost its advanced packaging output, plus, there are two plants planned to be constructed in the United States, both in Arizona, as part of its 12-fab Expansion plan.
We have already seen reports that NVIDIA will move advanced packaging orders to Intel for its next-gen Feynman GPUs. These are anticipated to utilize Chipzilla's improved EMIB technology. But at the same time, the spillover effect for orders might benefit TSMC as it focuses on the more profitable processes and its high-end customers, which is if those customers don't end up moving to competitors entirely.
About the author: A Software Engineer by training and a PC enthusiast by passion, Hassan Mujtaba serves as Wccftech's Senior Editor for hardware section. With years of experience in the industry, he specializes in deep-dive technical analysis of next-generation CPU and GPU architectures, motherboards, and cooling solutions. His work involves not only breaking news on upcoming technologies but also extensive hands-on reviews and benchmarking.
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